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Date:   Fri, 10 Feb 2023 16:36:02 -0800
From:   Jakub Kicinski <kuba@...nel.org>
To:     Hariprasad Kelam <hkelam@...vell.com>
Cc:     <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <davem@...emloft.net>, <pabeni@...hat.com>, <edumazet@...gle.com>,
        <sgoutham@...vell.com>, <lcherian@...vell.com>,
        <gakula@...vell.com>, <jerinj@...vell.com>, <sbhatta@...vell.com>,
        <jhs@...atatu.com>, <xiyou.wangcong@...il.com>, <jiri@...nulli.us>,
        <saeedm@...dia.com>, <richardcochran@...il.com>,
        <tariqt@...dia.com>, <linux-rdma@...r.kernel.org>,
        <maxtram95@...il.com>, <naveenm@...vell.com>,
        <bpf@...r.kernel.org>, <hariprasad.netdev@...il.com>
Subject: Re: [net-next Patch V4 0/4] octeontx2-pf: HTB offload support

On Fri, 10 Feb 2023 16:40:47 +0530 Hariprasad Kelam wrote:
> octeontx2 silicon and CN10K transmit interface consists of five
> transmit levels starting from MDQ, TL4 to TL1. Once packets are
> submitted to MDQ, hardware picks all active MDQs using strict
> priority, and MDQs having the same priority level are chosen using
> round robin. Each packet will traverse MDQ, TL4 to TL1 levels.
> Each level contains an array of queues to support scheduling and
> shaping.
> 
> As HTB supports classful queuing mechanism by supporting rate and
> ceil and allow the user to control the absolute bandwidth to
> particular classes of traffic the same can be achieved by
> configuring shapers and schedulers on different transmit levels.

Please provide or link to some user-facing documentation under
Documentation/networking/device_drivers/ethernet/marvell/octeon...

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