netdev - Re: [PATCH net-next v3 3/7] octeon_ep: control mailbox for multiple PFs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 14 Feb 2023 18:49:04 +0100
From:   Maciej Fijalkowski <maciej.fijalkowski@...el.com>
To:     Veerasenareddy Burru <vburru@...vell.com>
CC:     <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <aayarekar@...vell.com>, <sedara@...vell.com>,
        <sburla@...vell.com>, <linux-doc@...r.kernel.org>,
        "David S. Miller" <davem@...emloft.net>,
        "Eric Dumazet" <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v3 3/7] octeon_ep: control mailbox for multiple
 PFs

On Mon, Feb 13, 2023 at 09:14:18PM -0800, Veerasenareddy Burru wrote:
> Add control mailbox support for multiple PFs.
> Update control mbox base address calculation based on PF function link.
> 
> Signed-off-by: Veerasenareddy Burru <vburru@...vell.com>
> Signed-off-by: Abhijit Ayarekar <aayarekar@...vell.com>
> ---
> v2 -> v3:
>  * no change
> 
> v1 -> v2:
>  * no change
> 
>  .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c   | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> index f40ebac15a79..c82a1347eed8 100644
> --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> @@ -13,6 +13,9 @@
>  #include "octep_main.h"
>  #include "octep_regs_cn9k_pf.h"
>  
> +#define CTRL_MBOX_MAX_PF	128
> +#define CTRL_MBOX_SZ		((size_t)(0x400000 / CTRL_MBOX_MAX_PF))
> +
>  /* Names of Hardware non-queue generic interrupts */
>  static char *cn93_non_ioq_msix_names[] = {
>  	"epf_ire_rint",
> @@ -199,6 +202,8 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)
>  	struct octep_config *conf = oct->conf;
>  	struct pci_dev *pdev = oct->pdev;
>  	u64 val;
> +	int pos;
> +	u8 link = 0;

RCT again

>  
>  	/* Read ring configuration:
>  	 * PF ring count, number of VFs and rings per VF supported
> @@ -234,7 +239,16 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)
>  	conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;
>  	conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names;
>  
> -	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + (0x400000ull * 7);
> +	pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV);
> +	if (pos) {
> +		pci_read_config_byte(oct->pdev,
> +				     pos + PCI_SRIOV_FUNC_LINK,
> +				     &link);
> +		link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);
> +	}
> +	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr +
> +					   (0x400000ull * 8) +

can you explain why s/7/8 and was it broken previously?

> +					   (link * CTRL_MBOX_SZ);
>  }
>  
>  /* Setup registers for a hardware Tx Queue  */
> -- 
> 2.36.0
>