netdev - Re: [net-next PATCH] octeontx2-af: Add NIX Errata workaround on CN10K silicon

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Message-ID: <Y/HpLEx3Ebh+IegK@unreal>
Date:   Sun, 19 Feb 2023 11:17:32 +0200
From:   Leon Romanovsky <leon@...nel.org>
To:     Sai Krishna <saikrishnag@...vell.com>
Cc:     davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
        pabeni@...hat.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, sgoutham@...vell.com,
        gakula@...vell.com
Subject: Re: [net-next PATCH] octeontx2-af: Add NIX Errata workaround on
 CN10K silicon

On Fri, Feb 17, 2023 at 11:21:12AM +0530, Sai Krishna wrote:
> From: Geetha sowjanya <gakula@...vell.com>
> 
> This patch adds workaround for below 2 HW erratas
> 
> 1. Due to improper clock gating, NIXRX may free the same
> NPA buffer multiple times.. to avoid this, always enable
> NIX RX conditional clock.
> 
> 2. NIX FIFO does not get initialized on reset, if the SMQ
> flush is triggered before the first packet is processed, it
> will lead to undefined state. The workaround to perform SMQ
> flush only if packet count is non-zero in MDQ.
> 
> Signed-off-by: Geetha sowjanya <gakula@...vell.com>
> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@...vell.com>
> Signed-off-by: Sai Krishna <saikrishnag@...vell.com>
> ---
>  .../net/ethernet/marvell/octeontx2/af/rvu.h    |  3 +++
>  .../ethernet/marvell/octeontx2/af/rvu_cn10k.c  | 18 ++++++++++++++++++
>  .../ethernet/marvell/octeontx2/af/rvu_nix.c    | 10 ++++++++++
>  .../ethernet/marvell/octeontx2/af/rvu_reg.h    |  2 ++
>  4 files changed, 33 insertions(+)

Just curious, why aren't these erratas coded as PCI quirks?

Thanks