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Date: Mon, 20 Feb 2023 16:00:57 +0100
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: Yanhong Wang <yanhong.wang@...rfivetech.com>
Cc: linux-riscv@...ts.infradead.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Richard Cochran <richardcochran@...il.com>,
Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Peter Geis <pgwipeout@...il.com>
Subject: Re: [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add ethernet device node
On Mon, 20 Feb 2023 at 15:22, Emil Renner Berthing
<emil.renner.berthing@...onical.com> wrote:
> On Wed, 18 Jan 2023 at 07:19, Yanhong Wang
> <yanhong.wang@...rfivetech.com> wrote:
> > Add JH7110 ethernet device node to support gmac driver for the JH7110
> > RISC-V SoC.
> >
> > Signed-off-by: Yanhong Wang <yanhong.wang@...rfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++
> > 1 file changed, 93 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index c22e8f1d2640..c6de6e3b1a25 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -433,5 +433,98 @@
> > reg-shift = <2>;
> > status = "disabled";
> > };
> > +
> > + stmmac_axi_setup: stmmac-axi-config {
> > + snps,lpi_en;
> > + snps,wr_osr_lmt = <4>;
> > + snps,rd_osr_lmt = <4>;
> > + snps,blen = <256 128 64 32 0 0 0>;
> > + };
> > +
> > + gmac0: ethernet@...30000 {
> > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
> > + reg = <0x0 0x16030000 0x0 0x10000>;
> > + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
> > + <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
> > + <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
> > + <&aoncrg JH7110_AONCLK_GMAC0_TX>,
>
> The gmac0_tx clock is a mux that takes either the gmac0_gtxclk or
> rmii_rtx as parent. However it is then followed by an inverter that
> optionally inverts the clock, gmac0_tx_inv. I'm guessing this
> optionally inverted signal is what is actually used (otherwise why
> would the inverter exist), so I think this clock is what should be
> claimed here. Eg.
> <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
>
> Right now it works only because the inverted signal can't be gated
> (turned off) even when it's not claimed by any driver.
>
> > + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>,
> > + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
>
> Here the gmac0_gtxclk clock is the parent of the gmac0_gtxc, so
> claiming the gmac0_gtxc should be enough. Since the gmac0_gtxc is just
> a gate it should have the CLK_SET_RATE_PARENT flag set, so the driver
> can just change the rate of the child and it should propagate to the
> parent. In short I think claiming only the gmac0_gtxc clock should be
> enough here.
Oh and just for completeness. This also goes for gmac1 below, and
don't forget to update the yaml binding doc accordingly.
> > + clock-names = "stmmaceth", "pclk", "ptp_ref",
> > + "tx", "gtxc", "gtx";
> > + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
> > + <&aoncrg JH7110_AONRST_GMAC0_AHB>;
> > + reset-names = "stmmaceth", "ahb";
> > + interrupts = <7>, <6>, <5>;
> > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
> > + phy-mode = "rgmii-id";
> > + snps,multicast-filter-bins = <64>;
> > + snps,perfect-filter-entries = <8>;
> > + rx-fifo-depth = <2048>;
> > + tx-fifo-depth = <2048>;
> > + snps,fixed-burst;
> > + snps,no-pbl-x8;
> > + snps,force_thresh_dma_mode;
> > + snps,axi-config = <&stmmac_axi_setup>;
> > + snps,tso;
> > + snps,en-tx-lpi-clockgating;
> > + snps,txpbl = <16>;
> > + snps,rxpbl = <16>;
> > + status = "disabled";
> > + phy-handle = <&phy0>;
> > +
> > + mdio0: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + phy0: ethernet-phy@0 {
> > + reg = <0>;
> > + };
> > + };
> > + };
> > +
> > + gmac1: ethernet@...40000 {
> > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
> > + reg = <0x0 0x16040000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
> > + <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
> > + <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
> > + <&syscrg JH7110_SYSCLK_GMAC1_TX>,
> > + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>,
> > + <&syscrg JH7110_SYSCLK_GMAC1_GTXCLK>;
> > + clock-names = "stmmaceth", "pclk", "ptp_ref",
> > + "tx", "gtxc", "gtx";
> > + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
> > + <&syscrg JH7110_SYSRST_GMAC1_AHB>;
> > + reset-names = "stmmaceth", "ahb";
> > + interrupts = <78>, <77>, <76>;
> > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
> > + phy-mode = "rgmii-id";
> > + snps,multicast-filter-bins = <64>;
> > + snps,perfect-filter-entries = <8>;
> > + rx-fifo-depth = <2048>;
> > + tx-fifo-depth = <2048>;
> > + snps,fixed-burst;
> > + snps,no-pbl-x8;
> > + snps,force_thresh_dma_mode;
> > + snps,axi-config = <&stmmac_axi_setup>;
> > + snps,tso;
> > + snps,en-tx-lpi-clockgating;
> > + snps,txpbl = <16>;
> > + snps,rxpbl = <16>;
> > + status = "disabled";
> > + phy-handle = <&phy1>;
> > +
> > + mdio1: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + phy1: ethernet-phy@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > };
> > };
> > --
> > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
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