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Message-ID: <20230222193440.c2vzg7j7r32xwr5l@skbuf>
Date: Wed, 22 Feb 2023 21:34:40 +0200
From: Vladimir Oltean <olteanv@...il.com>
To: Arınç ÜNAL <arinc.unal@...nc9.com>
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
netdev <netdev@...r.kernel.org>, erkin.bozoglu@...ont.com,
Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>,
Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Landen Chao <Landen.Chao@...iatek.com>,
Sean Wang <sean.wang@...iatek.com>,
DENG Qingfang <dqfext@...il.com>
Subject: Re: Choose a default DSA CPU port
On Wed, Feb 22, 2023 at 09:08:03PM +0300, Arınç ÜNAL wrote:
> On 22.02.2023 21:06, Vladimir Oltean wrote:
> > On Wed, Feb 22, 2023 at 06:17:42PM +0100, Frank Wunderlich wrote:
> > > without Arincs Patch i got 940Mbit on gmac0, so something seems to affect the gmac when port5 is enabled.
> >
> > which patch?
>
> I believe Frank is referring to the patch series I submitted which adds
> port@5 to Bananapi BPI-R2. Without the patch, gmac0 is the default DSA
> master.
>
> https://lore.kernel.org/linux-mediatek/20230210182505.24597-1-arinc.unal@arinc9.com/
>
> Arınç
And with your patch + my patch, gmac0 is still the default DSA master,
but gmac1/port5 are also enabled. The claim is that switch port 6/gmac0
has lower bandwidth when switch port 5/gmac1 is enabled, than when it isn't?
Frank's testing is done on the MT7623 SoC (with the MT7530 switch),
an SoC which you have access to, since you've submitted those device
tree changes, correct? Do you confirm his result?
The posted ethtool stats are not sufficient to determine the cause of
the issue. It would be necessary to see all non-zero Ethernet counters
on both CPU port pairs:
ethtool -S eth0 | grep -v ': 0'
ethtool -S eth1 | grep -v ': 0'
to determine whether the cause of the performance degradation is packet
loss or just a lossless slowdown of some sorts. For example, the
degradation might be caused by the added flow control + uncalibrated
watermarks, not by the activation of the other GMAC.
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