netdev - Re: [PATCH net 1/3] net: dsa: seville: ignore mscc-miim read errors from Lynx PCS

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Date:   Fri, 24 Feb 2023 10:37:37 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Vladimir Oltean <vladimir.oltean@....com>, netdev@...r.kernel.org
Cc:     "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Claudiu Manoil <claudiu.manoil@....com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        UNGLinuxDriver@...rochip.com, Andrew Lunn <andrew@...n.ch>,
        Colin Foster <colin.foster@...advantage.com>,
        Lee Jones <lee@...nel.org>,
        Maksim Kiselev <bigunclemax@...il.com>,
        Maxim Kochetkov <fido_max@...ox.ru>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>
Subject: Re: [PATCH net 1/3] net: dsa: seville: ignore mscc-miim read errors
 from Lynx PCS

On 2/24/23 07:52, Vladimir Oltean wrote:
> During the refactoring in the commit below, vsc9953_mdio_read() was
> replaced with mscc_miim_read(), which has one extra step: it checks for
> the MSCC_MIIM_DATA_ERROR bits before returning the result.
> 
> On T1040RDB, there are 8 QSGMII PCSes belonging to the switch, and they
> are organized in 2 groups. First group responds to MDIO addresses 4-7
> because QSGMIIACR1[MDEV_PORT] is 1, and the second group responds to
> MDIO addresses 8-11 because QSGMIIBCR1[MDEV_PORT] is 2. I have double
> checked that these values are correctly set in the SERDES, as well as
> PCCR1[QSGMA_CFG] and PCCR1[QSGMB_CFG] are both 0b01.
> 
> mscc_miim_read: phyad 8 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 8 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 8 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 8 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 9 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 9 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 9 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 9 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 10 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 10 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 10 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 10 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 11 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 11 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 11 reg 0x1 MIIM_DATA 0x2d
> mscc_miim_read: phyad 11 reg 0x5 MIIM_DATA 0x5801
> mscc_miim_read: phyad 4 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 4 reg 0x5 MIIM_DATA 0x3da01, ERROR
> mscc_miim_read: phyad 5 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 5 reg 0x5 MIIM_DATA 0x35801, ERROR
> mscc_miim_read: phyad 5 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 5 reg 0x5 MIIM_DATA 0x35801, ERROR
> mscc_miim_read: phyad 6 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 6 reg 0x5 MIIM_DATA 0x35801, ERROR
> mscc_miim_read: phyad 6 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 6 reg 0x5 MIIM_DATA 0x35801, ERROR
> mscc_miim_read: phyad 7 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 7 reg 0x5 MIIM_DATA 0x35801, ERROR
> mscc_miim_read: phyad 7 reg 0x1 MIIM_DATA 0x3002d, ERROR
> mscc_miim_read: phyad 7 reg 0x5 MIIM_DATA 0x35801, ERROR
> 
> As can be seen, the data in MIIM_DATA is still valid despite having the
> MSCC_MIIM_DATA_ERROR bits set. The driver as introduced in commit
> 84705fc16552 ("net: dsa: felix: introduce support for Seville VSC9953
> switch") was ignoring these bits, perhaps deliberately (although
> unbeknownst to me).
> 
> This is an old IP and the hardware team cannot seem to be able to help
> me track down a plausible reason for these failures. I'll keep
> investigating, but in the meantime, this is a direct regression which
> must be restored to a working state.
> 
> The only thing I can do is keep ignoring the errors as before.
> 
> Fixes: b99658452355 ("net: dsa: ocelot: felix: utilize shared mscc-miim driver for indirect MDIO access")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
-- 
Florian