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Date: Fri, 3 Mar 2023 16:59:25 +0800 From: Samin Guo <samin.guo@...rfivetech.com> To: <linux-riscv@...ts.infradead.org>, <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org> CC: "David S . Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Emil Renner Berthing <kernel@...il.dk>, Richard Cochran <richardcochran@...il.com>, Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, Peter Geis <pgwipeout@...il.com>, Yanhong Wang <yanhong.wang@...rfivetech.com>, Samin Guo <samin.guo@...rfivetech.com> Subject: [PATCH v5 09/12] riscv: dts: starfive: jh7110: Add syscon to support phy interface settings The phy interface needs to be set in syscon, the format is as follows: starfive,syscon: <&syscon, offset, mask> Signed-off-by: Samin Guo <samin.guo@...rfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 2ce28292b721..c1c5085dab72 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -554,6 +554,7 @@ snps,en-tx-lpi-clockgating; snps,txpbl = <16>; snps,rxpbl = <16>; + starfive,syscon = <&aon_syscon 0xc 0x1c0000>; status = "disabled"; phy-handle = <&phy0>; @@ -596,6 +597,7 @@ snps,en-tx-lpi-clockgating; snps,txpbl = <16>; snps,rxpbl = <16>; + starfive,syscon = <&sys_syscon 0x90 0x1c>; status = "disabled"; phy-handle = <&phy1>; -- 2.17.1
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