netdev - Re: [PATCH v5 08/12] net: stmmac: starfive

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <52822ce5-0712-48e5-81e0-c6ac09d6a6ee@lunn.ch>
Date:   Mon, 6 Mar 2023 14:06:20 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc:     Guo Samin <samin.guo@...rfivetech.com>,
        linux-riscv@...ts.infradead.org, netdev@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        "David S . Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Richard Cochran <richardcochran@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Peter Geis <pgwipeout@...il.com>,
        Yanhong Wang <yanhong.wang@...rfivetech.com>
Subject: Re: [PATCH v5 08/12] net: stmmac: starfive_dmac: Add phy interface
 settings

> Ugh, you're right. Both the syscon block, the register offset and the
> bit position in those registers are different from gmac0 to gmac1, and
> since we need a phandle to the syscon block anyway passing those two
> other parameters as arguments is probably the nicest solution. For the
> next version I'd change the 2nd argument from mask to the bit position
> though. It seems the field is always 3 bits wide and this makes it a
> little clearer that we're not just putting register values in the
> device tree.

I prefer bit position over mask.

But please fully document this in the device tree. This is something a
board developer is going to get wrong, because they assume MAC blocks
are identical, and normally need identical configuration.

I assume this is also a hardware 'bug', and the next generation of the
silicon will have this fixed? So this will go away?

	Andrew