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Message-ID: <BN7PR12MB2802A2E7A193B8BC0073812BDCB79@BN7PR12MB2802.namprd12.prod.outlook.com>
Date: Tue, 7 Mar 2023 11:09:41 +0000
From: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>
To: Jonas Gorski <jonas.gorski@...il.com>
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Subject: RE: [PATCH V5 09/15] spi: Add stacked and parallel memories support
in SPI core
Hello,
> -----Original Message-----
> From: Jonas Gorski <jonas.gorski@...il.com>
> Sent: Tuesday, March 7, 2023 1:31 AM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@....com>
> Cc: broonie@...nel.org; miquel.raynal@...tlin.com; richard@....at;
> vigneshr@...com; jic23@...nel.org; tudor.ambarus@...rochip.com;
> pratyush@...nel.org; Mehta, Sanju <Sanju.Mehta@....com>; chin-
> ting_kuo@...eedtech.com; clg@...d.org; kdasu.kdev@...il.com;
> f.fainelli@...il.com; rjui@...adcom.com; sbranden@...adcom.com;
> eajames@...ux.ibm.com; olteanv@...il.com; han.xu@....com;
> john.garry@...wei.com; shawnguo@...nel.org; s.hauer@...gutronix.de;
> narmstrong@...libre.com; khilman@...libre.com;
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> Subject: Re: [PATCH V5 09/15] spi: Add stacked and parallel memories
> support in SPI core
>
> Hi,
>
> On Mon, 6 Mar 2023 at 18:26, Amit Kumar Mahapatra <amit.kumar-
> mahapatra@....com> wrote:
> >
> > For supporting multiple CS the SPI device need to be aware of all the
> > CS values. So, the "chip_select" member in the spi_device structure is
> > now an array that holds all the CS values.
> >
> > spi_device structure now has a "cs_index_mask" member. This acts as an
> > index to the chip_select array. If nth bit of spi->cs_index_mask is
> > set then the driver would assert spi->chip_select[n].
> >
> > In parallel mode all the chip selects are asserted/de-asserted
> > simultaneously and each byte of data is stored in both devices, the
> > even bits in one, the odd bits in the other. The split is
> > automatically handled by the GQSPI controller. The GQSPI controller
> > supports a maximum of two flashes connected in parallel mode. A
> > "multi-cs-cap" flag is added in the spi controntroller data, through
> > ctlr->multi-cs-cap the spi core will make sure that the controller is
> > capable of handling multiple chip selects at once.
> >
> > For supporting multiple CS via GPIO the cs_gpiod member of the
> > spi_device structure is now an array that holds the gpio descriptor
> > for each chipselect.
> >
> > Multi CS support using GPIO is not tested due to unavailability of
> > necessary hardware setup.
> >
> > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> mahapatra@....com>
> > ---
> > drivers/spi/spi.c | 213 +++++++++++++++++++++++++++-------------
> > include/linux/spi/spi.h | 34 +++++--
> > 2 files changed, 173 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > 5866bf5813a4..8ec7f58fa111 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -613,7 +613,8 @@ static int spi_dev_check(struct device *dev, void
> *data)
> > struct spi_device *new_spi = data;
> >
> > if (spi->controller == new_spi->controller &&
> > - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> > + spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0) &&
> > + spi_get_chipselect(spi, 1) == spi_get_chipselect(new_spi,
> > + 1))
> > return -EBUSY;
>
> This will only reject new devices if both chip selects are identical, but not if
> they only share one, e.g. CS 1 + 2 vs 1 + 3, or 1 + 2 vs only 2, or if the order is
> different (1 + 2 vs 2 + 1 - haven't read the code too close to know if this is
> allowed/possible).
Agreed, will add in the next series.
Regards,
Amit
>
> Regards,
> Jonas
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