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Message-ID: <214954598c1155557eab714bd4b89f04b60d2f34.camel@mediatek.com>
Date: Thu, 9 Mar 2023 03:21:51 +0000
From: Garmin Chang (張家銘)
<Garmin.Chang@...iatek.com>
To: "wenst@...omium.org" <wenst@...omium.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mturquette@...libre.com" <mturquette@...libre.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"sboyd@...nel.org" <sboyd@...nel.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"richardcochran@...il.com" <richardcochran@...il.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support
On Fri, 2023-02-03 at 15:35 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:58 PM Garmin.Chang <
> Garmin.Chang@...iatek.com> wrote:
> >
> > Add MT8188 vppsys1 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@...iatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-vpp1.c | 138
> > +++++++++++++++++++++++++
> > 2 files changed, 139 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 48deecc6b520..37663de293bf 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > - clk-mt8188-vpp0.o
> > + clk-mt8188-vpp0.o clk-mt8188-
> > vpp1.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > new file mode 100644
> > index 000000000000..2bff3a52c93f
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@...iatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> > + .set_ofs = 0x104,
> > + .clr_ofs = 0x108,
> > + .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> > + .set_ofs = 0x114,
> > + .clr_ofs = 0x118,
> > + .sta_ofs = 0x110,
> > +};
> > +
> > +#define GATE_VPP1_0(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP1_1(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp1_clks[] = {
> > + /* VPP1_0 */
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl",
> > "top_vpp", 0),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc",
> > "top_vpp", 1),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot",
> > "top_vpp", 2),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad",
> > "top_vpp", 3),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot",
> > "top_vpp", 4),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad",
> > "top_vpp", 5),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot",
> > "top_vpp", 6),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad",
> > "top_vpp", 7),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma",
> > "top_vpp", 8),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg",
> > "top_vpp", 9),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma",
> > "top_vpp", 10),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg",
> > "top_vpp", 11),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma",
> > "top_vpp", 12),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg",
> > "top_vpp", 13),
> > + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split",
> > "top_vpp", 14),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY,
> > "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz",
> > "top_vpp", 16),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP,
> > "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR,
> > "vpp1_svpp1_mdp_color", "top_vpp", 18),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY,
> > "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz",
> > "top_vpp", 20),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE,
> > "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP,
> > "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR,
> > "vpp1_svpp2_mdp_color", "top_vpp", 23),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz",
> > "top_vpp", 24),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE,
> > "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP,
> > "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR,
> > "vpp1_svpp3_mdp_color", "top_vpp", 27),
> > + GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> > + GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> > + GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> > + GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> > + /* VPP1_1 */
> > + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr",
> > "top_vpp", 0),
> > + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal",
> > "top_vpp", 1),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr",
> > "top_vpp", 2),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal",
> > "top_vpp", 3),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr",
> > "top_vpp", 4),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal",
> > "top_vpp", 5),
> > + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex",
> > "top_vpp", 7),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY,
> > "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY,
> > "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> > + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async",
> > "top_vpp", 10),
> > + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay",
> > "top_vpp", 11),
> > + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng",
> > "top_vpp", 12),
> > + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng",
> > "top_vpp", 13),
> > + GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta",
> > "top_vpp", 16),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi",
> > "top_vpp", 17),
> > + GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> > + GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp",
> > 19),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi",
> > "top_vpp", 20),
> > + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ",
> > "top_vpp", 21),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m",
> > "top_vpp", 26),
> > +};
> > +
> > +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->parent->of_node;
> > + struct clk_hw_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_gates(node, vpp1_clks,
> > ARRAY_SIZE(vpp1_clks), clk_data);
>
> Same here. Please update.
Thank you for your suggestions.
OK. I'll moidfy it in v6.
>
> Once fixed,
>
> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
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