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Message-ID: <20230310173217.3429788-16-amit.kumar-mahapatra@amd.com>
Date: Fri, 10 Mar 2023 23:02:17 +0530
From: Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>
To: <broonie@...nel.org>, <miquel.raynal@...tlin.com>,
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Subject: [PATCH V6 15/15] spi: spi-zynqmp-gqspi: Add parallel memories support in GQSPI driver
During GQSPI driver probe set ctlr->multi-cs-cap for enabling multi CS
capability of the controller. In parallel mode the controller can either
split the data between both the flash or can send the same data to both the
flashes, this is determined by the STRIPE bit. While sending commands to
the flashes the GQSPI driver send the same command to both the flashes by
resetting the STRIPE bit, but while writing/reading data to & from the
flash the GQSPI driver splits the data evenly between both the flashes by
setting the STRIPE bit.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>
---
drivers/spi/spi-zynqmp-gqspi.c | 39 +++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 3d2b92a88e8a..d795d17d2541 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -23,6 +23,7 @@
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
/* Generic QSPI register offsets */
#define GQSPI_CONFIG_OFST 0x00000100
@@ -192,6 +193,7 @@ struct qspi_platform_data {
* @op_lock: Operational lock
* @speed_hz: Current SPI bus clock speed in hz
* @has_tapdelay: Used for tapdelay register available in qspi
+ * @is_parallel: Used for multi CS support
*/
struct zynqmp_qspi {
struct spi_controller *ctlr;
@@ -214,8 +216,33 @@ struct zynqmp_qspi {
struct mutex op_lock;
u32 speed_hz;
bool has_tapdelay;
+ bool is_parallel;
};
+/**
+ * zynqmp_gqspi_update_stripe - For GQSPI controller data stripe capabilities
+ * @op: Pointer to mem ops
+ * Return: Status of the data stripe
+ *
+ * Returns true if data stripe need to be enabled, else returns false
+ */
+bool zynqmp_gqspi_update_stripe(const struct spi_mem_op *op)
+{
+ if (op->cmd.opcode == SPINOR_OP_BE_4K ||
+ op->cmd.opcode == SPINOR_OP_BE_32K ||
+ op->cmd.opcode == SPINOR_OP_CHIP_ERASE ||
+ op->cmd.opcode == SPINOR_OP_SE ||
+ op->cmd.opcode == SPINOR_OP_BE_32K_4B ||
+ op->cmd.opcode == SPINOR_OP_SE_4B ||
+ op->cmd.opcode == SPINOR_OP_BE_4K_4B ||
+ op->cmd.opcode == SPINOR_OP_WRSR ||
+ op->cmd.opcode == SPINOR_OP_BRWR ||
+ (op->cmd.opcode == SPINOR_OP_WRSR2 && !op->addr.nbytes))
+ return false;
+
+ return true;
+}
+
/**
* zynqmp_gqspi_read - For GQSPI controller read operation
* @xqspi: Pointer to the zynqmp_qspi structure
@@ -470,7 +497,14 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
- if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
+ if ((qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) &&
+ (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS)) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ if (!xqspi->is_parallel)
+ xqspi->is_parallel = true;
+ } else if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
zynqmp_gqspi_selectslave(xqspi,
GQSPI_SELECT_FLASH_CS_UPPER,
GQSPI_SELECT_FLASH_BUS_LOWER);
@@ -1139,6 +1173,8 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem,
}
if (op->data.nbytes) {
+ if (xqspi->is_parallel && zynqmp_gqspi_update_stripe(op))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
reinit_completion(&xqspi->data_completion);
if (op->data.dir == SPI_MEM_DATA_OUT) {
xqspi->txbuf = (u8 *)op->data.buf.out;
@@ -1334,6 +1370,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
ctlr->dev.of_node = np;
ctlr->auto_runtime_pm = true;
+ ctlr->multi_cs_cap = true;
ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret) {
--
2.25.1
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