netdev - Re: [PATCH v6 06/13] x86/hyperv: Change vTOM handling to use standard coco mechanisms

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Message-ID: <20230320181646.GAZBijDiAckZ9WOmhU@fat_crate.local>
Date:   Mon, 20 Mar 2023 19:16:46 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     "Michael Kelley (LINUX)" <mikelley@...rosoft.com>
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Subject: Re: [PATCH v6 06/13] x86/hyperv: Change vTOM handling to use
 standard coco mechanisms

On Mon, Mar 20, 2023 at 01:30:54PM +0000, Michael Kelley (LINUX) wrote:
> In a vTOM VM, CPUID leaf 0x8000001f is filtered so it does *not* return
> Bit 1 (SEV) as set.  Consequently, sme_enable() does not read MSR_AMD64_SEV
> and does not populate sev_status.

So how much of the hardware side of vTOM are you actually using besides
the actual encryption?

Virtual TOM MSR (C001_0135)? Anything else?

AFAICT, you're passing the vTOM value from CPUID from the hypervisor so
I'm guessing that happens underneath in the hypervisor?

I'd like to make sure there are no more "surprises" down the road...

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette