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Message-ID: <20230330114631.6afa041c@pc-7.home>
Date:   Thu, 30 Mar 2023 11:46:31 +0200
From:   Maxime Chevallier <maxime.chevallier@...tlin.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Mark Brown <broonie@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        rafael@...nel.org, Colin Foster <colin.foster@...advantage.com>,
        Vladimir Oltean <vladimir.oltean@....com>,
        Lee Jones <lee@...nel.org>, davem@...emloft.net,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        thomas.petazzoni@...tlin.com
Subject: Re: [RFC 4/7] mfd: ocelot-spi: Change the regmap stride to reflect
 the real one

Hello Andrew,

On Mon, 27 Mar 2023 02:02:55 +0200
Andrew Lunn <andrew@...n.ch> wrote:

> > > >  static const struct regmap_config ocelot_spi_regmap_config = {
> > > >  	.reg_bits = 24,
> > > > -	.reg_stride = 4,
> > > > +	.reg_stride = 1,
> > > >  	.reg_shift = REGMAP_DOWNSHIFT(2),
> > > >  	.val_bits = 32,    
> > > 
> > > This does not look like a bisectable change? Or did it never work
> > > before?  
> > 
> > Actually this works in all cases because of "regmap: check for
> > alignment on translated register addresses" in this series. Before
> > this series, I think using a stride of 1 would have worked too, as
> > any 4-byte-aligned accesses are also 1-byte aligned.  
> 
> This is the sort of think which is good to explain in the commit
> message. That is the place to answer questions reviewers are likely to
> ask for things which are not obvious from just the patch.

That's right, I will include this explanation in the next iteration.
Thanks for the review,

Maxime

>     Andrew

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