netdev - Re: [PATCH net-next 2/6] net: txgbe: Implement I2C bus master driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <3086ecbc-2884-4743-9953-96f2a225ddbb@lunn.ch>
Date:   Tue, 4 Apr 2023 16:18:59 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Jiawen Wu <jiawenwu@...stnetic.com>
Cc:     netdev@...r.kernel.org, linux@...linux.org.uk,
        mengyuanlou@...-swift.com
Subject: Re: [PATCH net-next 2/6] net: txgbe: Implement I2C bus master driver

On Tue, Apr 04, 2023 at 10:47:28AM +0800, Jiawen Wu wrote:
> On Monday, April 3, 2023 8:53 PM, Andrew Lunn wrote:
> > On Mon, Apr 03, 2023 at 02:45:24PM +0800, Jiawen Wu wrote:
> > > I2C bus is integrated in Wangxun 10Gb ethernet chip. Implement I2C bus
> > > driver to receive I2C messages.
> > 
> > Please Cc: the i2c mailing list for comments. They know more about I2C than
> the
> > netdev people.
> > 
> > Is the I2C bus master your own IP, or have you licensed a core? Or using the
> open
> > cores i2C bus master? I just want to make sure there is not already a linux
> driver for
> > this.
> > 
> 
> I use the I2C core driver, and implement my own i2c_algorithm. I think it needs
> to configure my registers to realize the function.

I had a quick look, and it appears the hardware is not an open-cores
derived I2C bus master.

As i tried to say, sometimes you just license an I2C bus master,
rather than develop one from scratch. And if it was a licensed IP
core, there is likely to be an existing driver.

> > > +	if (!read) {
> > > +		wx_err(wx, "I2C write not supported\n");
> > > +		return num_msgs;
> > > +	}
> > 
> > Write is not supported at all? Is this a hardware limitation?  I think
> -EOPNOTSUPP
> > is required here, and you need to ensure the code using the I2C bus master has
> > quirks to not try to write.
> 
> It is supported. False testing leads to false perceptions, I'll fix it.

Great. It would be odd not having write support.

	Andrew