netdev - Re: [PATCH 00/12] Rework PHY reset handling

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Message-ID: <20230405144218.kl7dqtms4x534jvi@pengutronix.de>
Date:   Wed, 5 Apr 2023 16:42:18 +0200
From:   Marco Felsch <m.felsch@...gutronix.de>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Broadcom internal kernel review list 
        <bcm-kernel-feedback-list@...adcom.com>,
        Richard Cochran <richardcochran@...il.com>,
        Radu Pirea <radu-nicolae.pirea@....nxp.com>,
        Shyam Sundar S K <Shyam-sundar.S-k@....com>,
        Yisen Zhuang <yisen.zhuang@...wei.com>,
        Salil Mehta <salil.mehta@...wei.com>,
        Jassi Brar <jaswinder.singh@...aro.org>,
        Ilias Apalodimas <ilias.apalodimas@...aro.org>,
        Iyappan Subramanian <iyappan@...amperecomputing.com>,
        Keyur Chudgar <keyur@...amperecomputing.com>,
        Quan Nguyen <quan@...amperecomputing.com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Len Brown <lenb@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Frank Rowand <frowand.list@...il.com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org,
        devicetree@...r.kernel.org, kernel@...gutronix.de
Subject: Re: [PATCH 00/12] Rework PHY reset handling

Hi Florian,

On 23-04-05, Florian Fainelli wrote:
> Hi Marco,
> 
> On 4/5/2023 2:26 AM, Marco Felsch wrote:
> > The current phy reset handling is broken in a way that it needs
> > pre-running firmware to setup the phy initially. Since the very first
> > step is to readout the PHYID1/2 registers before doing anything else.
> > 
> > The whole dection logic will fall apart if the pre-running firmware
> > don't setup the phy accordingly or the kernel boot resets GPIOs states
> > or disables clocks. In such cases the PHYID1/2 read access will fail and
> > so the whole detection will fail.
> 
> PHY reset is a bit too broad and should need some clarifications between:
> 
> - external reset to the PHY whereby a hardware pin on the PHY IC may be used
> 
> - internal reset to the PHY whereby we call into the PHY driver soft_reset
> function to have the PHY software reset itself
> 
> You are changing the way the former happens, not the latter, at least not
> changing the latter intentionally if at all.

Yes.

> This is important because your cover letter will be in the merge commit in
> the networking tree.

Ah okay, I didn't know that. I will adapt the cover letter accordingly.

> Will do a more thorough review on a patch by patch basis. Thanks.

Thanks a lot, looking forward to it.

Regards,
  Marco