netdev - Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

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Message-ID: <b5e96d31-6290-44e5-b829-737e40f0ef35@lunn.ch>
Date:   Fri, 7 Apr 2023 18:10:31 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Vladimir Oltean <vladimir.oltean@....com>
Cc:     shawnguo@...nel.org, s.hauer@...gutronix.de,
        Russell King <rmk+kernel@...linux.org.uk>,
        arm-soc <arm@...nel.org>, netdev <netdev@...r.kernel.org>
Subject: Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

On Fri, Apr 07, 2023 at 06:41:59PM +0300, Vladimir Oltean wrote:
> On Fri, Apr 07, 2023 at 05:25:01PM +0200, Andrew Lunn wrote:
> > The DSA framework has got more picky about always having a phy-mode
> > for the CPU port. The imx51 Ethernet supports MII, and RMII. Set the
> > switch phy-mode based on how the SoC Ethernet port has been
> > configured.
> > 
> > Additionally, the cpu label has never actually been used in the
> > binding, so remove it.
> > 
> > Signed-off-by: Andrew Lunn <andrew@...n.ch>
> > ---
> 
> In theory, an MII MAC-to-MAC connection should have phy-mode = "mii" on
> one end and phy-mode = "rev-mii" on the other, right?

In theory, yes. As far as i understand, it makes a difference to where
the clock comes from. rev-mii is a clock provider i think.

But from what i understand of the code, and the silicon, this property
is going to be ignored, whatever value you give it. phy-mode is only
used and respected when the port can support 1000Base-X, SGMII, and
above, or use its built in PHY. For MII, GMII, RMII, RGMII the port
setting is determined by strapping resistors.

The DSA core however does care that there is a phy-mode, even if it is
ignored. I hope after these patches land we can turn that check into
enforce mode, and that then unlocks Russell to make phylink
improvement.

	Andrew