netdev - Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

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Date:   Mon, 10 Apr 2023 11:37:15 +0100
From:   "Russell King (Oracle)" <linux@...linux.org.uk>
To:     Vladimir Oltean <vladimir.oltean@....com>
Cc:     Andrew Lunn <andrew@...n.ch>, shawnguo@...nel.org,
        s.hauer@...gutronix.de, arm-soc <arm@...nel.org>,
        netdev <netdev@...r.kernel.org>
Subject: Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

On Mon, Apr 10, 2023 at 01:00:12PM +0300, Vladimir Oltean wrote:
> On Fri, Apr 07, 2023 at 06:10:31PM +0200, Andrew Lunn wrote:
> > On Fri, Apr 07, 2023 at 06:41:59PM +0300, Vladimir Oltean wrote:
> > > In theory, an MII MAC-to-MAC connection should have phy-mode = "mii" on
> > > one end and phy-mode = "rev-mii" on the other, right?
> > 
> > In theory, yes. As far as i understand, it makes a difference to where
> > the clock comes from. rev-mii is a clock provider i think.
> > 
> > But from what i understand of the code, and the silicon, this property
> > is going to be ignored, whatever value you give it. phy-mode is only
> > used and respected when the port can support 1000Base-X, SGMII, and
> > above, or use its built in PHY. For MII, GMII, RMII, RGMII the port
> > setting is determined by strapping resistors.
> > 
> > The DSA core however does care that there is a phy-mode, even if it is
> > ignored. I hope after these patches land we can turn that check into
> > enforce mode, and that then unlocks Russell to make phylink
> > improvement.
> 
> Actually, looking at mv88e6xxx_translate_cmode() right now, I guess it's
> not exactly true that the value is going to be ignored, whatever it is.
> A CMODE of MV88E6XXX_PORT_STS_CMODE_MII_PHY is not going to be translated
> into "rev-mii", but into "mii", same as MV88E6XXX_PORT_STS_CMODE_MII.
> Same for MV88E6XXX_PORT_STS_CMODE_RMII_PHY ("rmii" and not "rev-rmii").
> So, when given "rev-mii" or "rev-rmii" as phy modes in the device tree,
> the generic phylink validation procedure should reject them for being
> unsupported.
> 
> This means either the patch set moves forward with v1, or the driver is
> fixed to accept the dedicated PHY modes for PHY roles.
> 
> Russell, what do you think?

I'm afraid I didn't bother trying to understand all the *MII modes
that Marvell document poorly in their functional specification,
especially when they document that e.g. RMII_PHY mode can also be
used to connect to a PHY. I took their table with a pinch of salt
and did what I thought was best.

It is entirely possible that some are wrong, especially as we don't
document what the various PHY_INTERFACE_MODE_* mean in the kernel
(remember that I started doing that).

As far as phylink, it treats REV*MII and the corresponding *MII
mode the same way in terms of their capabilities, but as you say
it will determine which mode will be acceptable.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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