netdev - Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

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Message-ID: <c4b386af-2a51-4690-b552-e1da074e06d2@lunn.ch>
Date:   Mon, 10 Apr 2023 14:35:28 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Vladimir Oltean <vladimir.oltean@....com>
Cc:     Russell King <rmk+kernel@...linux.org.uk>, shawnguo@...nel.org,
        s.hauer@...gutronix.de, arm-soc <arm@...nel.org>,
        netdev <netdev@...r.kernel.org>
Subject: Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode

On Mon, Apr 10, 2023 at 01:00:12PM +0300, Vladimir Oltean wrote:
> On Fri, Apr 07, 2023 at 06:10:31PM +0200, Andrew Lunn wrote:
> > On Fri, Apr 07, 2023 at 06:41:59PM +0300, Vladimir Oltean wrote:
> > > In theory, an MII MAC-to-MAC connection should have phy-mode = "mii" on
> > > one end and phy-mode = "rev-mii" on the other, right?
> > 
> > In theory, yes. As far as i understand, it makes a difference to where
> > the clock comes from. rev-mii is a clock provider i think.
> > 
> > But from what i understand of the code, and the silicon, this property
> > is going to be ignored, whatever value you give it. phy-mode is only
> > used and respected when the port can support 1000Base-X, SGMII, and
> > above, or use its built in PHY. For MII, GMII, RMII, RGMII the port
> > setting is determined by strapping resistors.
> > 
> > The DSA core however does care that there is a phy-mode, even if it is
> > ignored. I hope after these patches land we can turn that check into
> > enforce mode, and that then unlocks Russell to make phylink
> > improvement.
> 
> Actually, looking at mv88e6xxx_translate_cmode() right now, I guess it's
> not exactly true that the value is going to be ignored, whatever it is.
> A CMODE of MV88E6XXX_PORT_STS_CMODE_MII_PHY is not going to be translated
> into "rev-mii", but into "mii", same as MV88E6XXX_PORT_STS_CMODE_MII.
> Same for MV88E6XXX_PORT_STS_CMODE_RMII_PHY ("rmii" and not "rev-rmii").
> So, when given "rev-mii" or "rev-rmii" as phy modes in the device tree,
> the generic phylink validation procedure should reject them for being
> unsupported.

I tested vf610-zii-devel-rev-c.dtb:

[    2.307416] mv88e6085 mdio_mux-0.1:00: configuring for fixed/rev-rmii link mode
[    2.314459] mv88e6085 mdio_mux-0.1:00: configuring for fixed/xaui link mode
[    2.320588] mv88e6085 mdio_mux-0.1:00: Link is Up - 100Mbps/Full - flow control off
[    2.327722] mv88e6085 mdio_mux-0.2:00: configuring for fixed/xaui link mode
[    2.334729] mv88e6085 mdio_mux-0.2:00: Link is Up - 10Gbps/Full - flow control off
[    2.343263] mv88e6085 mdio_mux-0.1:00: Link is Up - 10Gbps/Full - flow control off
[    2.396110] mv88e6085 mdio_mux-0.1:00 lan1 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:01] driver [Marvell 88E6390 Fa)
[    2.498137] mv88e6085 mdio_mux-0.1:00 lan2 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:02] driver [Marvell 88E6390 Fa)
[    2.566028] mv88e6085 mdio_mux-0.1:00 lan3 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:03] driver [Marvell 88E6390 Fa)
[    2.663995] mv88e6085 mdio_mux-0.1:00 lan4 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:04] driver [Marvell 88E6390 Fa)
[    2.746064] mv88e6085 mdio_mux-0.2:00 lan5 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:01] driver [Marvell 88E6390 Fa)
[    2.834000] mv88e6085 mdio_mux-0.2:00 lan6 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:02] driver [Marvell 88E6390 Fa)
[    2.933998] mv88e6085 mdio_mux-0.2:00 lan7 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:03] driver [Marvell 88E6390 Fa)
[    3.016031] mv88e6085 mdio_mux-0.2:00 lan8 (uninitialized): PHY [!mdio-mux!mdio@...witch@...dio:04] driver [Marvell 88E6390 Fa)
[    3.033976] mv88e6085 mdio_mux-0.2:00 sff2 (uninitialized): switched to inband/2500base-x link mode

So we can see link mode rev-rmii and there are no errors.

Testing a board using mii, not rmii is going to be a bit harder. I
don't have one set up right now.

      Andrew