netdev - Re: [PATCH 2/3] staging: octeon: avoid needless device allocation

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Message-ID: <ZD0TPvDa7zopm0dx@lenoch>
Date:   Mon, 17 Apr 2023 11:37:02 +0200
From:   Ladislav Michl <oss-lists@...ops.cz>
To:     Dan Carpenter <error27@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>, linux-staging@...ts.linux.dev,
        netdev@...r.kernel.org, linux-mips@...r.kernel.org,
        Chris Packham <chris.packham@...iedtelesis.co.nz>
Subject: Re: [PATCH 2/3] staging: octeon: avoid needless device allocation

On Mon, Apr 17, 2023 at 11:37:30AM +0300, Dan Carpenter wrote:
> On Thu, Apr 13, 2023 at 07:20:08PM +0200, Andrew Lunn wrote:
> > > I was asking this question myself and then came to this:
> > > Converting driver to phylink makes separating different macs easier as
> > > this driver is splitted between staging and arch/mips/cavium-octeon/executive/
> > > However I'll provide changes spotted previously as separate preparational
> > > patches. Would that work for you?
> > 
> > Is you end goal to get this out of staging? phylib vs phylink is not a
> > reason to keep it in staging.
> > 
> > It just seems odd to be adding new features to a staging driver. As a
> > bit of a "carrot and stick" maybe we should say you cannot add new
> > features until it is ready to move out of staging?
> 
> We already have that rule.  But I don't know anything about phy vs
> phylink...

Let me elaborate here a bit then.

Current Octeon driver comes from Cavium's vendor kernel tree. Cavium
started this about two decades ago based on their own ideas and tries
to bend kernel interfaces around them.

Driver is based aroud Packet Input Processing/Input Packet Data (PIP/IPD)
units which can connect their data streams to various interfaces.
SGMII/1000BASE-X/QSGMII and RGMII are just two of them.

Currently driver iterates over all interfaces and all ports to bind
interfaces to PIP/IPD. There is a lot of code deciding which
interfaces/ports exits on given Octeon SoC, see
arch/mips/cavium-octeon/executive/
Driver code then calls those helpers with interface/port aguments
and they do the magic using switches deciding what to do based
on interface type.

I'm proposing to leave all that trickery behind and just follow what's
written in device tree, so each I/O interface ends up as a driver
with its own mac ops. While it is possible to implement that as
private mac ops as some other drivers do, I think it is more
convenient to use phylink_mac_ops.

In case I'm missing something or I'm wrong with analysis, please let
me know.

Thanks,
	ladis