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Message-ID: <ZEKtHbO+gPcakNur@corigine.com>
Date: Fri, 21 Apr 2023 17:34:53 +0200
From: Simon Horman <simon.horman@...igine.com>
To: Ramón Nordin Rodriguez
<ramon.nordin.rodriguez@...roamp.se>
Cc: Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
Vladimir Oltean <olteanv@...il.com>
Subject: Re: [PATCH v4] drivers/net/phy: add driver for Microchip LAN867x
10BASE-T1S PHY
On Thu, Apr 20, 2023 at 06:36:38PM +0200, Ramón Nordin Rodriguez wrote:
> This patch adds support for the Microchip LAN867x 10BASE-T1S family
> (LAN8670/1/2). The driver supports P2MP with PLCA.
>
> Signed-off-by: Ramón Nordin Rodriguez <ramon.nordin.rodriguez@...roamp.se>
...
> +static int lan867x_config_init(struct phy_device *phydev)
> +{
> + /* HW quirk: Microchip states in the application note (AN1699) for the phy
> + * that a set of read-modify-write (rmw) operations has to be performed
> + * on a set of seemingly magic registers.
> + * The result of these operations is just described as 'optimal performance'
> + * Microchip gives no explanation as to what these mmd regs do,
> + * in fact they are marked as reserved in the datasheet.
> + * It is unclear if phy_modify_mmd would be safe to use or if a write
> + * really has to happen to each register.
> + * In order to exacly conform to what is stated in the AN phy_write_mmd is
nit: s/exacly/exactly/
> + * used, which might then write the same value back as read + modified.
> + */
...
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