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Message-ID: <9626e30c-9e0c-b182-4c2e-1ec6c0c98c9e@linux.intel.com>
Date: Fri, 21 Apr 2023 09:52:02 +0300
From: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
To: Jiawen Wu <jiawenwu@...stnetic.com>, 'Andrew Lunn' <andrew@...n.ch>
Cc: netdev@...r.kernel.org, linux@...linux.org.uk,
linux-i2c@...r.kernel.org, linux-gpio@...r.kernel.org,
olteanv@...il.com, mengyuanlou@...-swift.com
Subject: Re: [PATCH net-next v3 2/8] i2c: designware: Add driver support for
Wangxun 10Gb NIC
On 4/20/23 13:29, Jiawen Wu wrote:
> On Thursday, April 20, 2023 4:58 AM, Andrew Lunn wrote:
>> On Wed, Apr 19, 2023 at 04:27:33PM +0800, Jiawen Wu wrote:
>>> Wangxun 10Gb ethernet chip is connected to Designware I2C, to communicate
>>> with SFP.
>>>
>>> Add platform data to pass IOMEM base address, board flag and other
>>> parameters, since resource address was mapped on ethernet driver.
>>>
>>> The exists IP limitations are dealt as workarounds:
>>> - IP does not support interrupt mode, it works on polling mode.
>>> - I2C cannot read continuously, only one byte can at a time.
>>
>> Are you really sure about that?
>>
>> It is a major limitation for SFP devices. It means you cannot access
>> the diagnostics, since you need to perform an atomic 2 byte read.
>>
>> Or maybe i'm understanding you wrong.
>>
>> Andrew
>>
>
> Maybe I'm a little confused about this. Every time I read a byte info, I have to
> write a 'read command'. It can normally get the information for SFP devices.
> But I'm not sure if this is regular I2C behavior.
>
I agree, IC_DATA_CMD operation is obscure. In order to read from the
bus, writes with BIT(8) set is required into IC_DATA_CMD, wait
(irq/poll) DW_IC_INTR_RX_FULL is set in DW_IC_RAW_INTR_STAT and then
read back received data from IC_DATA_CMD while taking into count FIFO sizes.
Full documentation of this IP is in DesignWare DW_apb_i2c Databook. You
may try to get access to Synopsys or try to find if older version of it
is available somewhere.
https://www.synopsys.com/dw/ipdir.php?c=DW_apb_i2c
Plain register specifications can be found from some of the Intel
datasheets. For example chapter 13.2 I2C Memory Mapped Registers
Summary, page 667 in a datasheet below:
https://cdrdv2-public.intel.com/743845/743845_001.pdf
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