Message-ID: <340234b8-91d3-3c1e-b985-9a2298b377aa@mistywest.com>
Date:   Fri, 21 Apr 2023 17:28:32 -0700
From:   Ron Eggler <ron.eggler@...tywest.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Heiner Kallweit <hkallweit1@...il.com>, netdev@...r.kernel.org,
        Russell King - ARM Linux <linux@...linux.org.uk>
Subject: Re: issues to bring up two VSC8531 PHYs

On 4/21/23 09:35, Andrew Lunn wrote:
>>> You can also try:
>>>
>>> ethtool --phy-statistics ethX
>> after appliaction of the above patch, ethtool tells me
>>
>> # ethtool --phy-statistics eth0
>> PHY statistics:
>>       phy_receive_errors: 65535
>>      phy_idle_errors: 255
> So these have saturated. Often these counters don't wrap, they stop at
> the maximum value.
>
> These errors also indicate your problem is probably not between the
> MAC and the PHY, but between the PHY and the RJ45 socket. Or maybe how
> the PHY is clocked. It might not have a stable clock, or the wrong
> clock frequency.

Oh and as for the clock, there's a 25MHz, +/- 20ppm  crystal hooked up 
to XTAL1 & XTAL2 pins which is a supported clock source (per datasheet) 
but I also see in the following:

For RGMII mode: Configure register 20E2 (to access register 20E2, 
register 31 must be set to 2).
Set bit 11 to 0 and set RX_CLK delay and TX_CLK delay accordingly 
through bit [6:4] and/or bit [2:0]
respectively.

I figured out that the register 20E2 is in the extended register space 
which is accessible when register 0x1F is set to 0x0002. I've been able 
to set and read it, I found a nice loop from David Creger that reads the 
complete register space and prints it to stdout:

# x=0; while  [ $x -le 31 ]; do printf  "Register 0x%02X = " $x ; 
phytool read eth0/0/$x  $(( x++ )) ; done
Register 0x00 = 0x1040
Register 0x01 = 0x796d
Register 0x02 = 0x0007
Register 0x03 = 0x0572
Register 0x04 = 0x0101
Register 0x05 = 0x45e1
Register 0x06 = 0x0005
Register 0x07 = 0x2801
Register 0x08 = 0000
Register 0x09 = 0x0200
Register 0x0A = 0x4000
Register 0x0B = 0000
Register 0x0C = 0000
Register 0x0D = 0000
Register 0x0E = 0000
Register 0x0F = 0x3000
Register 0x10 = 0x028e
Register 0x11 = 0x0100
Register 0x12 = 0x0800
Register 0x13 = 0000
Register 0x14 = 0000
Register 0x15 = 0000
Register 0x16 = 0000
Register 0x17 = 0000
Register 0x18 = 0000
Register 0x19 = 0000
Register 0x1A = 0000
Register 0x1B = 0x0ff0
Register 0x1C = 0000
Register 0x1D = 0000
Register 0x1E = 0x0030
Register 0x1F = 0x0002

and per the datasheet, the extended registers space maps into the above 
registers 16 - 30 like:

Address Name
16E2 Cu PMD Transmit Control
17E2 EEE Control
18E2–19E2 Reserved
20E2 RGMII Control
21E2 Wake-on-LAN MAC Address [15:0]
22E2 Wake-on-LAN MAC Address [31:16]
23E2 Wake-on-LAN MAC Address [47:32]
24E2 Secure-On Password [15:0]
25E2 Secure-On Password [31:16]
26E2 Secure-On Password [47:32]
27E2 Wake-on-LAN and MAC Interface Control
28E2 Extended Interrupt Mask
29E2 Extended Interrupt Status
30E2 Reserved

So per my calculations:

Register 0x10 = -> 16E2
Register 0x11 = -> 17E2
Register 0x12 = -> 18E2
Register 0x13 = -> 19E2
Register 0x14 = -> 20E2
Register 0x15 = -> 21E2
Register 0x16 = -> 22E2
Register 0x17 = -> 23E2
Register 0x18 = -> 24E2
Register 0x19 = -> 25E2
Register 0x1A = -> 26E2
Register 0x1B = -> 27E2
Register 0x1C = -> 28E2
Register 0x1D = -> 29E2
Register 0x1E = -> 30E2

20 (0x14) maps into 20E2 but I'm not fully certain what RX_CLK and 
TX_CLK should be set to, can anyone help me out, here?

datasheet: 
https://www.microchip.com/content/dam/mchp/documents/OTH/ProductDocuments/DataSheets/VMDS-10514.pdf

Also, should the above delay configuration not be part of the driver and 
configurable through the device tree?

https://www.kernel.org/doc/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt

-- 
RON EGGLER Firmware Engineer (he/him/his) www.mistywest.com

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