netdev - Re: [PATCH v4 2/2] pinctrl: qcom: Add SDX75 pincontrol driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <ZEk9lySMZcrRZYwX@surfacebook>
Date:   Wed, 26 Apr 2023 18:04:55 +0300
From:   andy.shevchenko@...il.com
To:     Rohit Agarwal <quic_rohiagar@...cinc.com>
Cc:     agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
        linus.walleij@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, richardcochran@...il.com,
        manivannan.sadhasivam@...aro.org, linux-arm-msm@...r.kernel.org,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH v4 2/2] pinctrl: qcom: Add SDX75 pincontrol driver

Mon, Apr 24, 2023 at 02:33:50PM +0530, Rohit Agarwal kirjoitti:
> Add initial Qualcomm SDX75 pinctrl driver to support pin configuration
> with pinctrl framework for SDX75 SoC.
> While at it, reordering the SDX65 entry.

...

> +#define FUNCTION(fname)							\
> +	[msm_mux_##fname] = {						\
> +		.name = #fname,						\
> +		.groups = fname##_groups,				\
> +	.ngroups = ARRAY_SIZE(fname##_groups),				\
> +	}

PINCTRL_PINFUNCTION() ?

...

> +static const struct of_device_id sdx75_pinctrl_of_match[] = {
> +	{.compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl}, {},

One entry per line.
And drop comma in the terminator one.

> +};

No MODULE_DEVICE_TABLE()?

-- 
With Best Regards,
Andy Shevchenko