netdev - Re: [PATCH net-next 2/2] net: phy: microchip_t1s: add support for Microchip LAN865x Rev.B0 PHYs

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Message-ID: <4d98e994-722c-2b72-4884-54247f8858ba@microchip.com>
Date:   Thu, 27 Apr 2023 14:23:04 +0000
From:   <Parthiban.Veerasooran@...rochip.com>
To:     <andrew@...n.ch>
CC:     <netdev@...r.kernel.org>, <davem@...emloft.net>,
        <Jan.Huber@...rochip.com>, <Thorsten.Kummermehr@...rochip.com>,
        <ramon.nordin.rodriguez@...roamp.se>
Subject: Re: [PATCH net-next 2/2] net: phy: microchip_t1s: add support for
 Microchip LAN865x Rev.B0 PHYs

Hi Andrew,

On 27/04/23 3:32 am, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
>> +     /* disable all the interrupts
>> +      */
>> +     ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_IRQ_1_CTL, 0xFFFF);
>> +     if (ret)
>> +             return ret;
>> +     return phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_IRQ_2_CTL, 0xFFFF);
> 
> This is also something which could be in a patch of its own, with an
Ok noted.
> explanation in the commit message. You said the device will generate
> an interrupt after reset whatever. So it would be good to document
> this odd behaviour. Also, should you actually clear the pending
> interrupt, as well as disable interrupts? I assume there is an
> interrupt status register? It would typically be clear on read, or
> write 1 to clear a specific interrupt?
Yes, I checked in the datasheet timing diagram and it is recommended to 
clear the "reset done" interrupt in the lan867x rev.b1 before going for 
the initial configuration. It may not be needed for lan865x. I noticed, 
there is a slight change in handling the interrupt between lan867x and 
lan865x PHYs. I will double check and update the code accordingly.

Best Regards,
Parthiban V
> 
>          Andrew