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Message-ID: <6dd0ae37-9de9-c1fa-002c-b2b114b094a5@gmail.com> Date: Tue, 2 May 2023 11:24:01 -0700 From: Florian Fainelli <f.fainelli@...il.com> To: arinc9.unal@...il.com, Sean Wang <sean.wang@...iatek.com>, Landen Chao <Landen.Chao@...iatek.com>, DENG Qingfang <dqfext@...il.com>, Daniel Golle <daniel@...rotopia.org>, Andrew Lunn <andrew@...n.ch>, Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Matthias Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, René van Dorst <opensource@...rst.com> Cc: Arınç ÜNAL <arinc.unal@...nc9.com>, Bartel Eerdekens <bartel.eerdekens@...stell8.be>, Richard van Schagen <richard@...terhints.com>, Richard van Schagen <vschagen@...com>, Frank Wunderlich <frank-w@...lic-files.de>, mithat.guner@...ont.com, erkin.bozoglu@...ont.com, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org Subject: Re: [PATCH net 1/2] net: dsa: mt7530: fix corrupt frames using trgmii on 40 MHz XTAL MT7621 On 5/1/2023 5:15 AM, arinc9.unal@...il.com wrote: > From: Arınç ÜNAL <arinc.unal@...nc9.com> > > The multi-chip module MT7530 switch with a 40 MHz oscillator on the > MT7621AT, MT7621DAT, and MT7621ST SoCs forwards corrupt frames using > trgmii. > > This is caused by the assumption that MT7621 SoCs have got 150 MHz PLL, > hence using the ncpo1 value, 0x0780. > > My testing shows this value works on Unielec U7621-06, Bartel's testing > shows it won't work on Hi-Link HLK-MT7621A and Netgear WAC104. All devices > tested have got 40 MHz oscillators. > > Using the value for 125 MHz PLL, 0x0640, works on all boards at hand. The > definitions for 125 MHz PLL exist on the Banana Pi BPI-R2 BSP source code > whilst 150 MHz PLL don't. > > Forwarding frames using trgmii on the MCM MT7530 switch with a 25 MHz > oscillator on the said MT7621 SoCs works fine because the ncpo1 value > defined for it is for 125 MHz PLL. > > Change the 150 MHz PLL comment to 125 MHz PLL, and use the 125 MHz PLL > ncpo1 values for both oscillator frequencies. > > Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/81d24bbce7d99524d0771a8bdb2d6663e4eb4faa/u-boot-mt/drivers/net/rt2880_eth.c#L2195 > Fixes: 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") > Tested-by: Bartel Eerdekens <bartel.eerdekens@...stell8.be> > Tested-by: Arınç ÜNAL <arinc.unal@...nc9.com> > Signed-off-by: Arınç ÜNAL <arinc.unal@...nc9.com> Reviewed-by: Florian Fainelli <f.fainelli@...il.com> -- Florian
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