netdev - Re: [PATCH] net: stmmac: Initialize MAC_ONEUS_TIC

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Message-ID: <5ec678c0-9f4b-3d38-a0d8-700b5668e9c4@intel.com>
Date: Tue, 9 May 2023 16:46:01 -0700
From: Jesse Brandeburg <jesse.brandeburg@...el.com>
To: Marek Vasut <marex@...x.de>, <netdev@...r.kernel.org>
CC: "David S. Miller" <davem@...emloft.net>, Alexandre Torgue
	<alexandre.torgue@...s.st.com>, Eric Dumazet <edumazet@...gle.com>,
	"Francesco Dolcini" <francesco.dolcini@...adex.com>, Giuseppe Cavallaro
	<peppe.cavallaro@...com>, Harald Seiler <hws@...x.de>, Jakub Kicinski
	<kuba@...nel.org>, Jose Abreu <joabreu@...opsys.com>, Marcel Ziswiler
	<marcel.ziswiler@...adex.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Paolo Abeni <pabeni@...hat.com>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [PATCH] net: stmmac: Initialize MAC_ONEUS_TIC_COUNTER register

On 5/6/2023 4:58 PM, Marek Vasut wrote:
> Initialize MAC_ONEUS_TIC_COUNTER register with correct value derived
> from CSR clock, otherwise EEE is unstable on at least NXP i.MX8M Plus
> and Micrel KSZ9131RNX PHY, to the point where not even ARP request can
> be sent out.
> 
> i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
> 11.7.6.1.34 One-microsecond Reference Timer (MAC_ONEUS_TIC_COUNTER)
> defines this register as:
> "
> This register controls the generation of the Reference time (1 microsecond
> tic) for all the LPI timers. This timer has to be programmed by the software
> initially.
> ...
> The application must program this counter so that the number of clock cycles
> of CSR clock is 1us. (Subtract 1 from the value before programming).
> For example if the CSR clock is 100MHz then this field needs to be programmed
> to value 100 - 1 = 99 (which is 0x63).
> This is required to generate the 1US events that are used to update some of
> the EEE related counters.
> "
> 
> The reset value is 0x63 on i.MX8M Plus, which means expected CSR clock are
> 100 MHz. However, the i.MX8M Plus "enet_qos_root_clk" are 266 MHz instead,
> which means the LPI timers reach their count much sooner on this platform.
> 
> This is visible using a scope by monitoring e.g. exit from LPI mode on TX_CTL
> line from MAC to PHY. This should take 30us per STMMAC_DEFAULT_TWT_LS setting,
> during which the TX_CTL line transitions from tristate to low, and 30 us later
> from low to high. On i.MX8M Plus, this transition takes 11 us, which matches
> the 30us * 100/266 formula for misconfigured MAC_ONEUS_TIC_COUNTER register.
> 
> Configure MAC_ONEUS_TIC_COUNTER based on CSR clock, so that the LPI timers
> have correct 1us reference. This then fixes EEE on i.MX8M Plus with Micrel
> KSZ9131RNX PHY.
> 
> Signed-off-by: Marek Vasut <marex@...x.de>

Patch and commit message look good to me.

Reviewed-by: Jesse Brandeburg <jesse.brandeburg@...el.com>