netdev - Re: [PATCH net-next 5/5] net: mvneta: allocate TSO header DMA memory in chunks

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Message-ID: <ZFuEphwApIDwJSxb@shell.armlinux.org.uk>
Date: Wed, 10 May 2023 12:48:54 +0100
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Eric Dumazet <edumazet@...gle.com>
Cc: Marek Behún <kabel@...nel.org>,
	"David S. Miller" <davem@...emloft.net>,
	Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org,
	Paolo Abeni <pabeni@...hat.com>,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH net-next 5/5] net: mvneta: allocate TSO header DMA memory
 in chunks

On Wed, May 10, 2023 at 01:38:17PM +0200, Eric Dumazet wrote:
> On Wed, May 10, 2023 at 12:16 PM Russell King (Oracle)
> <rmk+kernel@...linux.org.uk> wrote:
> >
> > Now that we no longer need to check whether the DMA address is within
> > the TSO header DMA memory range for the queue, we can allocate the TSO
> > header DMA memory in chunks rather than one contiguous order-6 chunk,
> > which can stress the kernel's memory subsystems to allocate.
> >
> > Instead, use order-1 (8k) allocations, which will result in 32 order-1
> > pages containing 32 TSO headers.
> 
> I guess there is no IOMMU/SMMU/IOTLB involved on platforms using this driver.
> 
> (Otherwise, attempting high-order allocations, then fallback to
> low-order allocations
> would provide better performance if the high-order allocation at init
> time succeeded)

On the hardware I have, that is correct. Maybe others with mvneta on
different SoCs can comment? Thomas probably has an idea, but as he
hasn't worked on Marvell hardware for some time, may have forgotten
everything about Marvell hardware.

On that point, I'm wondering whether there's much value keeping
Thomas' maintainer's entries for Marvell stuff - any comment Thomas?

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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