netdev - Re: [PATCH 1/8] net: phy: realtek: rtl8221: allow to configure SERDES mode

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Message-ID: <81c3f04d-ec48-4ac0-ac16-b69dc6ae72e0@lunn.ch>
Date: Thu, 11 May 2023 02:41:07 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Daniel Golle <daniel@...rotopia.org>
Cc: netdev@...r.kernel.org, linux-mediatek@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Subject: Re: [PATCH 1/8] net: phy: realtek: rtl8221: allow to configure
 SERDES mode

> +#define RTL8221B_MMD_SERDES_CTRL		MDIO_MMD_VEND1
> +#define RTL8221B_MMD_PHY_CTRL			MDIO_MMD_VEND2

I suggest you don't do this. Use MDIO_MMD_VEND[1|2] to make it clear
these are vendor registers.

> +	case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
> +	case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
> +		break;
> +	case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
> +	case RTL8221B_SERDES_OPTION_MODE_HISGMII:
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
> +		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
> +		break;
> +	}

Is there anything in the datasheet to indicate register names and what
the values mean? It would be good to replace these magic values with
#defines.

	Andrew