netdev - Re: [PATCH net v2 2/3] net: dsa: rzn1-a5psw: fix STP states handling

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Message-ID: <7a2c205a-70dc-0d62-9e7b-cf09f7f5aac7@bootlin.com>
Date: Fri, 12 May 2023 08:33:52 +0200
From: Alexis Lothoré <alexis.lothore@...tlin.com>
To: Vladimir Oltean <olteanv@...il.com>
Cc: andrew@...n.ch, f.fainelli@...il.com, davem@...emloft.net,
 edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
 linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, thomas.petazzoni@...tlin.com,
 herve.codina@...tlin.com, miquel.raynal@...tlin.com,
 milan.stevanovic@...com, jimmy.lalande@...com, pascal.eberhard@...com
Subject: Re: [PATCH net v2 2/3] net: dsa: rzn1-a5psw: fix STP states handling

Hello Vladimir,
thanks for the fast review !
On 5/11/23 23:37, Vladimir Oltean wrote:
> On Thu, May 11, 2023 at 07:02:01PM +0200, alexis.lothore@...tlin.com wrote:
>> From: Clément Léger <clement.leger@...tlin.com>
>>
>> stp_set_state() should actually allow receiving BPDU while in LEARNING
>> mode which is not the case. Additionally, the BLOCKEN bit does not
>> actually forbid sending forwarded frames from that port. To fix this, add
>> a5psw_port_tx_enable() function which allows to disable TX. However, while
>> its name suggest that TX is totally disabled, it is not and can still
>> allow to send BPDUs even if disabled. This can be done by using forced
>> forwarding with the switch tagging mechanism but keeping "filtering"
>> disabled (which is already the case in the rzn1-a5sw tag driver). With
>> these fixes, STP support is now functional.
>>
>> Fixes: 888cdb892b61 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver")
>> Signed-off-by: Clément Léger <clement.leger@...tlin.com>
>> Signed-off-by: Alexis Lothoré <alexis.lothore@...tlin.com>
>> ---
> 
> Reviewed-by: Vladimir Oltean <olteanv@...il.com>
> 
>> @@ -344,28 +376,35 @@ static void a5psw_port_bridge_leave(struct dsa_switch *ds, int port,
>>  
>>  static void a5psw_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
>>  {
>> -	u32 mask = A5PSW_INPUT_LEARN_DIS(port) | A5PSW_INPUT_LEARN_BLOCK(port);
>>  	struct a5psw *a5psw = ds->priv;
>> -	u32 reg = 0;
>> +	bool learning_enabled, rx_enabled, tx_enabled;
> 
> Absolutely minor comment: in the networking subsystem there is a coding
> style preference to order lines with variable declarations longest to
> shortest (reverse Christmas tree). Since I don't see another less
> frivolous reason to resend the patch set, I thought I'd just mention
> for next time.

ACK. Since an error has been raised by CI bot on this series, I will send a V3
and fix this ordering too.

Regards,

-- 
Alexis Lothoré, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com