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Message-ID: <6643e099-7b72-4da2-aba1-521e1a4c961b@lunn.ch> Date: Thu, 18 May 2023 14:58:00 +0200 From: Andrew Lunn <andrew@...n.ch> To: Alexis Lothoré <alexis.lothore@...tlin.com> Cc: Florian Fainelli <f.fainelli@...il.com>, Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Richard Cochran <richardcochran@...il.com>, netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, thomas.petazzoni@...tlin.com, paul.arola@...us.com, scott.roberts@...us.com Subject: Re: [PATCH net-next 2/2] net: dsa: mv88e6xxx: enable support for 88E6361 switch > >> + [MV88E6361] = { > >> + .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, > >> + .family = MV88E6XXX_FAMILY_6393, > >> + .name = "Marvell 88E6361", > >> + .num_databases = 4096, > >> + .num_macs = 16384, > >> + .num_ports = 11, > >> + /* Ports 1, 2 and 8 are not routed */ > >> + .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), > >> + .num_internal_phys = 5, > > > > Which ports have internal PHYs? 2, 3, 4, 5, 6, 7 ? What does > > mv88e6xxx_phy_is_internal() return for these ports, and > > mv88e6xxx_get_capsmv88e6xxx_get_caps()? I'm wondering if you actually > > need to list 8 here? > > Indeed there is something wrong here too. I need to tune > mv88e6393x_phylink_get_caps to reflect 88E6361 differences. > > As stated above, port 3 to 7 are the ones with internal PHY. > For mv88e6xxx_phy_is_internal, I see that it is merely comparing the port index > to the number of internal phys, so in this case it would advertise (wrongly) > that ports 0 to 4 have internal phys. Ports 1 and 2 should hopefully be protected by the invalid_port_mask. It should not even be possible to create those ports. port 0 is interesting, and possibly currently broken on 6393. Please take a look at that. Andrew --- pw-bot: cr
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