netdev - Re: [PATCH net-next v4 1/2] net: dsa: microchip: ksz8: Make flow control, speed, and duplex on CPU port configurable

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Date: Fri, 19 May 2023 23:34:49 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Woojung Huh <woojung.huh@...rochip.com>, Andrew Lunn <andrew@...n.ch>,
	Arun Ramadoss <arun.ramadoss@...rochip.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Simon Horman <simon.horman@...igine.com>,
	"Russell King (Oracle)" <linux@...linux.org.uk>,
	linux-kernel@...r.kernel.org, UNGLinuxDriver@...rochip.com,
	Eric Dumazet <edumazet@...gle.com>, kernel@...gutronix.de,
	netdev@...r.kernel.org, Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	"David S. Miller" <davem@...emloft.net>
Subject: Re: [PATCH net-next v4 1/2] net: dsa: microchip: ksz8: Make flow
 control, speed, and duplex on CPU port configurable

On Fri, May 19, 2023 at 08:50:15PM +0200, Oleksij Rempel wrote:
> Thank you for your feedback. I see your point. 
> 
> We need to remember that the KSZ switch series has different types of
> ports. Specifically, for the KSZ8 series, there's a unique port. This
> port is unique because it's the only one that can be configured with
> global registers, and it is only one supports tail tagging. This special
> port is already referenced in the driver by "dev->cpu_port", so I continued
> using it in my patch.

Ok, I understand, so for the KSZ8 family, the assumption about which
port will use tail tagging is baked into the hardware.

> It is important to note that while this port has an xMII interface, it
> is not the only port that could have an xMII interface. Therefore, using
> "dev->info->internal_phy" may not be the best way to identify this port,
> because there can be ports that are not global/cpu, have an xMII
> interface, but don't have an internal PHY.

Right, but since we're talking about phylink, the goal is to identify
the xMII ports, not the CPU ports... This is a particularly denatured
case because the xMII port is global and is also the CPU port.