netdev - [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

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Message-Id: <20230520160603.32458-4-david.epping@missinglinkelectronics.com>
Date: Sat, 20 May 2023 18:06:03 +0200
From: David Epping <david.epping@...singlinkelectronics.com>
To: Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>
Cc: netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	UNGLinuxDriver@...rochip.com,
	David Epping <david.epping@...singlinkelectronics.com>
Subject: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

By default the VSC8501 and VSC8502 RGMII RX clock output is disabled.
To allow packet forwarding towards the MAC it needs to be enabled.
The same may be necessary for GMII and MII modes, but that's currently
unclear.

For VSC853x and VSC854x the respective disable bit is reserved and the
clock output is enabled by default.

Signed-off-by: David Epping <david.epping@...singlinkelectronics.com>
---
 drivers/net/phy/mscc/mscc.h      |  1 +
 drivers/net/phy/mscc/mscc_main.c | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index 79cbb2418664..defe5cc6d4fc 100644
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -179,6 +179,7 @@ enum rgmii_clock_delay {
 #define VSC8502_RGMII_CNTL		  20
 #define VSC8502_RGMII_RX_DELAY_MASK	  0x0070
 #define VSC8502_RGMII_TX_DELAY_MASK	  0x0007
+#define VSC8502_RGMII_RX_CLK_DISABLE	  0x0800
 
 #define MSCC_PHY_WOL_LOWER_MAC_ADDR	  21
 #define MSCC_PHY_WOL_MID_MAC_ADDR	  22
diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index 29fc27a16805..c7a8f5561c66 100644
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -547,6 +547,26 @@ static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
 	return rc;
 }
 
+/* For VSC8501 and VSC8502 the RGMII RX clock output is disabled by default. */
+static int vsc85xx_rgmii_enable_rx_clk(struct phy_device *phydev,
+				       u32 rgmii_cntl)
+{
+	int rc, phy_id;
+
+	phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
+	if (PHY_ID_VSC8501 != phy_id && PHY_ID_VSC8502 != phy_id)
+		return 0;
+
+	mutex_lock(&phydev->lock);
+
+	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, rgmii_cntl,
+			      VSC8502_RGMII_RX_CLK_DISABLE, 0);
+
+	mutex_unlock(&phydev->lock);
+
+	return rc;
+}
+
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
 	int rc;
@@ -559,6 +579,10 @@ static int vsc85xx_default_config(struct phy_device *phydev)
 					     VSC8502_RGMII_TX_DELAY_MASK);
 		if (rc)
 			return rc;
+
+		rc = vsc85xx_rgmii_enable_rx_clk(phydev, VSC8502_RGMII_CNTL);
+		if (rc)
+			return rc;
 	}
 
 	return 0;
-- 
2.17.1