netdev - Re: [PATCH net 0/3] net: phy: mscc: support VSC8501

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Message-ID: <20230521133330.qcr43rq2k7cxxtlt@skbuf>
Date: Sun, 21 May 2023 16:33:30 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: David Epping <david.epping@...singlinkelectronics.com>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	UNGLinuxDriver@...rochip.com
Subject: Re: [PATCH net 0/3] net: phy: mscc: support VSC8501

On Sat, May 20, 2023 at 06:06:00PM +0200, David Epping wrote:
> Since I can only test RGMII mode, and the register is called RGMII,
> my patch is limited to the RGMII mode. However, according to
> Microchip support (case number 01268776) this applies to all modes
> using the RX_CLK (which is all modes?).

I logged into my Microchip support account, but it looks like I can only
view cases which are mine. If they say that bit 11 applies to all PHY
modes where the PHY drives RX_CLK, that would mean MII, GMII and RGMII.

> Since the VSC8502 shares the same description, this would however mean
> the existing code for VSC8502 could have never worked.
> Is that possible? Has someone used VSC8502 successfully?

Yup (with U-Boot pre-initialization though). Thanks for the investigation.

> Other PHYs sharing the same basic code, like VSC8530/31/40/41 don't
> have the clock disabled and the bit 11 is reserved for them.
> Hence the check for PHY ID.
> 
> Should the uncertainty about GMII and MII modes be a source code
> comment? Or in the commit message? Or not mentioned at all?

I think we'd be better off moving the vsc85xx_rgmii_enable_rx_clk() call
outside the "if phy_interface_mode_is_rgmii(phydev->interface)" block,
if that's what Microchip support seems to suggest.