lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <20230522113331.36872-5-Parthiban.Veerasooran@microchip.com> Date: Mon, 22 May 2023 17:03:29 +0530 From: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com> To: <andrew@...n.ch>, <hkallweit1@...il.com>, <linux@...linux.org.uk>, <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>, <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <ramon.nordin.rodriguez@...roamp.se> CC: <horatiu.vultur@...rochip.com>, <Woojung.Huh@...rochip.com>, <Nicolas.Ferre@...rochip.com>, <Thorsten.Kummermehr@...rochip.com>, "Parthiban Veerasooran" <Parthiban.Veerasooran@...rochip.com> Subject: [PATCH net-next v2 4/6] net: phy: microchip_t1s: fix reset complete status handling As per the datasheet DS-LAN8670-1-2-60001573C.pdf, the Reset Complete status bit in the STS2 register to be checked before proceeding for the initial configuration. Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com> --- drivers/net/phy/microchip_t1s.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 869c7f403ea1..2f22a1954c09 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -14,6 +14,9 @@ #define LAN867X_REG_IRQ_1_CTL 0x001C #define LAN867X_REG_IRQ_2_CTL 0x001D +#define LAN867X_REG_STS2 0x0019 + +#define LAN867x_RESET_COMPLETE_STS BIT(11) /* The arrays below are pulled from the following table from AN1699 * Access MMD Address Value Mask @@ -65,6 +68,27 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) int err; + /* Read STS2 register and check for the Reset Complete status to do the + * init configuration. If the Reset Complete is not set, wait for 5us + * and then read STS2 register again and check for Reset Complete status. + * Still if it is failed then declare PHY reset error or else proceed + * for the PHY initial register configuration. + */ + err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); + if (err < 0) + return err; + + if (!(err & LAN867x_RESET_COMPLETE_STS)) { + udelay(5); + err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); + if (err < 0) + return err; + if (!(err & LAN867x_RESET_COMPLETE_STS)) { + phydev_err(phydev, "PHY reset failed\n"); + return -ENODEV; + } + } + /* Read-Modified Write Pseudocode (from AN1699) * current_val = read_register(mmd, addr) // Read current register value * new_val = current_val AND (NOT mask) // Clear bit fields to be written -- 2.34.1
Powered by blists - more mailing lists