netdev - Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

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Message-ID: <20230522095833.otk2nv24plmvarpt@skbuf>
Date: Mon, 22 May 2023 12:58:33 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: David Epping <david.epping@...singlinkelectronics.com>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	UNGLinuxDriver@...rochip.com
Subject: Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

On Sun, May 21, 2023 at 06:16:50PM +0200, David Epping wrote:
> Since we found an explanation why the current driver works in some
> setups (U-Boot), I would go with the Microchip support statement, that
> writing bit 11 to 0 is required in all modes.
> It would thus stay a separate function, called without a phy mode
> condition, and not be combined with the RGMII skew setting function.

If you still prefer to write twice in a row to the same paged register
instead of combining the changes, then fine by me, it's not a huge deal.