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Message-ID: <4b873053-38d8-f642-a5be-d9eba1f408fe@microchip.com> Date: Wed, 24 May 2023 07:25:16 +0000 From: <Parthiban.Veerasooran@...rochip.com> To: <andrew@...n.ch> CC: <hkallweit1@...il.com>, <linux@...linux.org.uk>, <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>, <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <ramon.nordin.rodriguez@...roamp.se>, <Horatiu.Vultur@...rochip.com>, <Woojung.Huh@...rochip.com>, <Nicolas.Ferre@...rochip.com>, <Thorsten.Kummermehr@...rochip.com> Subject: Re: [PATCH net-next v2 6/6] net: phy: microchip_t1s: add support for Microchip LAN865x Rev.B0 PHYs Hi Andrew, On 23/05/23 5:59 pm, Andrew Lunn wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >>> Is this doing a read from fuses? Is anything documented about this? >>> What the values mean? Would a board designer ever need to use >>> different values? Or is this just a case of 'trust us', you don't need >>> to understand this magic. >> Yes, it is a read from fuses and those values are specific/unique for >> each PHY chip. Those values are calculated based on some characteristics >> of the PHY chip behavior for optimal performance and they are fused in >> the PHY chip for the driver to configure it during the initialization. >> This is done in the production/testing stage of the PHY chip. As it is >> specific to PHY chip, a board designer doesn't have any influence on >> this and need not to worry about it. Unfortunately they can't be >> documented anywhere as they are design specific. So simply 'trust us'. > > O.K. Please consider for future generations that you move all this > magic into the PHY firmware. There does not seem to be any reason the > OS needs to know about this. Thanks for the feedback. Best Regards, Parthiban V > > Andrew
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