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Message-ID: <15fece9d-a716-44d6-bd88-876979acedf1@lunn.ch>
Date: Mon, 29 May 2023 22:11:12 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Conor Dooley <conor@...nel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, s.shtylyov@....ru,
davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
pabeni@...hat.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
geert+renesas@...der.be, magnus.damm@...il.com,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH net-next 1/5] dt-bindings: net: r8a779f0-ether-switch:
Add ACLK
On Mon, May 29, 2023 at 07:36:03PM +0100, Conor Dooley wrote:
> Hey,
>
> On Mon, May 29, 2023 at 05:08:36PM +0900, Yoshihiro Shimoda wrote:
> > Add ACLK of GWCA which needs to calculate registers' values for
> > rate limiter feature.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
> > ---
> > .../bindings/net/renesas,r8a779f0-ether-switch.yaml | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml b/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > index e933a1e48d67..cbe05fdcadaf 100644
> > --- a/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > +++ b/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > @@ -75,7 +75,12 @@ properties:
> > - const: rmac2_phy
> >
> > clocks:
> > - maxItems: 1
> > + maxItems: 2
> > +
> > + clock-names:
> > + items:
> > + - const: fck
> > + - const: aclk
>
> Since having both clocks is now required, please add some detail in the
> commit message about why that is the case. Reading it sounds like this
> is an optional new feature & not something that is required.
This is something i wondered about, backwards compatibility with old
DT blobs. In the C code it is optional, and has a default clock rate
if the clock is not present. So the yaml should not enforce an aclk
member.
Andrew
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