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Message-ID: <254978f3-3bf3-7cf5-e2b7-69d413acf092@linaro.org>
Date: Sun, 18 Jun 2023 20:47:07 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: niravkumar.l.rabara@...el.com, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
Dinh Nguyen <dinguyen@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>,
Wen Ping <wen.ping.teh@...el.com>, Richard Cochran
<richardcochran@...il.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
netdev@...r.kernel.org, Adrian Ng Ho Yin <adrian.ho.yin.ng@...el.com>
Subject: Re: [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible
On 18/06/2023 15:22, niravkumar.l.rabara@...el.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
>
> Add new compatible for Intel Agilex5 based boards.
>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> ---
> Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> index 4b4dcf551eb6..28849c720314 100644
> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> @@ -20,6 +20,7 @@ properties:
> - intel,n5x-socdk
> - intel,socfpga-agilex-n6000
> - intel,socfpga-agilex-socdk
> + - intel,socfpga-agilex5-socdk
> - const: intel,socfpga-agilex
This is agilex5, not agilex. Why are you using the same SoC compatible?
You have entire commit msg to explain your hardware and avoid such
questions...
Best regards,
Krzysztof
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