netdev - [PATCH 3/4] arm64: dts: qcom: sm8550: add UART14 nodes

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Message-Id: <20230620-topic-sm8550-upstream-bt-v1-3-4728564f8872@linaro.org>
Date: Tue, 20 Jun 2023 17:19:38 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: "David S. Miller" <davem@...emloft.net>, 
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, 
 Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Balakrishna Godavarthi <bgodavar@...eaurora.org>, 
 Rocky Liao <rjliao@...eaurora.org>, Marcel Holtmann <marcel@...tmann.org>, 
 Johan Hedberg <johan.hedberg@...il.com>, 
 Luiz Augusto von Dentz <luiz.dentz@...il.com>, 
 Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-bluetooth@...r.kernel.org, 
 linux-arm-msm@...r.kernel.org, Neil Armstrong <neil.armstrong@...aro.org>
Subject: [PATCH 3/4] arm64: dts: qcom: sm8550: add UART14 nodes

Add the Geni High Speed UART QUP instance 2 element 6
node and associated default pinctrl.

Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 41d60af93692..25dfc5fc5580 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1053,6 +1053,20 @@ spi13: spi@...000 {
 				status = "disabled";
 			};

+			uart14: uart@...000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x898000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
+				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
 			i2c15: i2c@...000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x0089c000 0 0x4000>;
@@ -3471,6 +3485,22 @@ qup_uart7_default: qup-uart7-default-state {
 				bias-disable;
 			};

+			qup_uart14_default: qup-uart14-default-state {
+				/* TX, RX */
+				pins = "gpio78", "gpio79";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+				/* CTS, RTS */
+				pins = "gpio76", "gpio77";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
 			sdc2_sleep: sdc2-sleep-state {
 				clk-pins {
 					pins = "sdc2_clk";

-- 
2.34.1