netdev - Re: [PATCH net-next 3/3] net: dsa: microchip: fix writes to phy registers >= 0x10

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Message-ID: <ZJHQYqbdTBKhZ0Vz@corigine.com>
Date: Tue, 20 Jun 2023 18:14:26 +0200
From: Simon Horman <simon.horman@...igine.com>
To: Rasmus Villemoes <linux@...musvillemoes.dk>
Cc: Woojung Huh <woojung.huh@...rochip.com>, UNGLinuxDriver@...rochip.com,
	Andrew Lunn <andrew@...n.ch>,
	Florian Fainelli <f.fainelli@...il.com>,
	Vladimir Oltean <olteanv@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 3/3] net: dsa: microchip: fix writes to phy
 registers >= 0x10

On Tue, Jun 20, 2023 at 01:38:54PM +0200, Rasmus Villemoes wrote:
> According to the errata sheets for ksz9477 and ksz9567, writes to the
> PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to
> 0xN13f) must be done as a 32 bit write to the 4-byte aligned address
> containing the register, hence requires a RMW in order not to change
> the adjacent PHY register.
> 
> Signed-off-by: Rasmus Villemoes <linux@...musvillemoes.dk>

Reviewed-by: Simon Horman <simon.horman@...igine.com>