netdev - [PATCH v2 1/1] net: axienet: Move reset before DMA detection

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Message-Id: <20230622175200.74033-1-fido_max@inbox.ru>
Date: Thu, 22 Jun 2023 20:52:00 +0300
From: Maxim Kochetkov <fido_max@...ox.ru>
To: netdev@...r.kernel.org
Cc: Maxim Kochetkov <fido_max@...ox.ru>,
	Radhey Shyam Pandey <radhey.shyam.pandey@....com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	Michal Simek <michal.simek@....com>,
	Andrew Lunn <andrew@...n.ch>,
	Robert Hancock <robert.hancock@...ian.com>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/1] net: axienet: Move reset before DMA detection

DMA detection will fail if axinet was started before (by boot loader,
boot ROM, etc). In this state axinet will not start properly.
XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to detect
64 DMA capability here. But datasheet says: When DMACR.RS is 1
(axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
is used to fetch the first descriptor. So iowrite32()/ioread32() trick
to this register to detect DMA will not work.
So move axinet reset before DMA detection.

Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO access")
Signed-off-by: Maxim Kochetkov <fido_max@...ox.ru>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 3e310b55bce2..734822321e0a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device *pdev)
 		goto cleanup_clk;
 	}
 
+	/* Reset core now that clocks are enabled, prior to accessing MDIO */
+	ret = __axienet_device_reset(lp);
+	if (ret)
+		goto cleanup_clk;
+
 	/* Autodetect the need for 64-bit DMA pointers.
 	 * When the IP is configured for a bus width bigger than 32 bits,
 	 * writing the MSB registers is mandatory, even if they are all 0.
@@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device *pdev)
 	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
 	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
 
-	/* Reset core now that clocks are enabled, prior to accessing MDIO */
-	ret = __axienet_device_reset(lp);
-	if (ret)
-		goto cleanup_clk;
-
 	ret = axienet_mdio_setup(lp);
 	if (ret)
 		dev_warn(&pdev->dev,
-- 
2.40.1