netdev - Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

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Date: Sun, 2 Jul 2023 18:00:36 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: <hkallweit1@...il.com>, <davem@...emloft.net>, <edumazet@...gle.com>,
        <kuba@...nel.org>, <pabeni@...hat.com>, <linux@...linux.org.uk>,
        <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link
 down



On 7/2/2023 12:21 AM, Andrew Lunn wrote:
>> Hi Andrew,
>> it is the PLL related registers, there is no PHY ID existed in MII register
>> 2, 3 of this block, so it can't be instantiated as the generic PHY device.
> 
> Well, phylib is going to scan those ID registers, and if it finds
> something other than 0xffff 0xffff in those two ID registers it is
> going to think a PHY is there. And then if there is no driver using
> that ID, it will instantiate a generic PHY.
> 
> You might be able to see this in /sys/bus/mdio_bus, especially if you
> don't have a DT node representing the MDIO bus.
> 
>        Andrew
Okay, understand it. thanks Andrew for pointing this.
i will check it.