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Message-ID: <CABikg9zfGVEJsWf7eq=K5oKQozt86LLn-rzMaVmycekXkQEa8Q@mail.gmail.com>
Date: Mon, 10 Jul 2023 17:35:35 +0300
From: Sergei Antonov <saproj@...il.com>
To: Vladimir Oltean <olteanv@...il.com>
Cc: netdev@...r.kernel.org, rmk+kernel@...linux.org.uk
Subject: Re: Regression: supported_interfaces filling enforcement
On Mon, 10 Jul 2023 at 15:35, Vladimir Oltean <olteanv@...il.com> wrote:
> > +static void mv88e6060_get_caps(struct dsa_switch *ds, int port,
> > + struct phylink_config *config)
> > +{
> > + __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
> > + __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
>
> This is enough to fix phylink generic validation on the front-facing
> ports with internal PHYs. But it is possible (and encouraged) to use
> phylink on the CPU port too (rev-mii, rev-rmii); currently that's not
> enforced for mv88e6060 because it's in the dsa_switches_apply_workarounds[]
> array.
>
> Could you please modify your device tree to add a fixed-link and
> phy-mode property on your CPU port so that phylink does get used
I already have fixed-link and phy-mode on CPU port. See below.
> , and
> populate supported_interfaces and mac_capabilities properly on the MII
> ports (4 and 5) as well (so that it doesn't fail validation)?
By setting bits in .phylink_get_caps function?
Should I remove mv88e6060 from dsa_switches_apply_workarounds too?
&mdio1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
switch@10 {
compatible = "marvell,mv88e6060";
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan2";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&mac1>;
phy-mode = "mii";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
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