netdev - Re: [PATCH net-next 2/7] net: pcs: xpcs: support to switch mode for Wangxun NICs

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Date: Tue, 25 Jul 2023 19:32:21 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Jiawen Wu <jiawenwu@...stnetic.com>
Cc: netdev@...r.kernel.org, hkallweit1@...il.com, linux@...linux.org.uk,
	Jose.Abreu@...opsys.com, mengyuanlou@...-swift.com
Subject: Re: [PATCH net-next 2/7] net: pcs: xpcs: support to switch mode for
 Wangxun NICs

> +static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)
> +{
> +	int val;
> +
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);
> +	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
> +	val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
> +	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
> +	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, 0xCF00);
> +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
> +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);
> +	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);
> +	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);
> +	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, 0x300);
> +	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, 0x300);
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, 0x600);
> +
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, 0x45);
> +	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
> +	val &= ~TXGBE_RX_EQ_ATTN_LVL0;
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
> +	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);

You have a lot of magic numbers above. Please truy to add some
#defines to try to explain what is going on here.

> +	val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE);
> +	val &= ~(TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0);
> +	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val);
> +	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4);
> +	val &= ~TXGBE_RX_EQ_CTL4_CONT_ADAPT0;
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val);
> +}
> +
> +static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)
> +{
> +	int val;
> +
> +	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
> +	val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
> +	val &= ~TXGBE_TX_GENCTL1_VBOOST_EN0;
> +	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
> +	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, 0xCF00);
> +
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, 0x7706);
> +	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
> +	val &= ~TXGBE_RX_EQ_ATTN_LVL0;
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
> +	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);
> +	val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3);
> +	val = u16_replace_bits(val, 0x4, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0);
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
> +
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);
> +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x540);
> +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x2A);
> +	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 0);
> +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, 0x10);
> +	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0x3);
> +	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0x3);
> +	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, 0x100);
> +	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, 0x100);
> +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, 0x200);
> +}
> +
> +static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs)
> +{
> +	int val, ret;
> +
> +	/* Wait xpcs power-up good */
> +	ret = read_poll_timeout(xpcs_read_vpcs, val,
> +				(val & DW_PSEQ_ST) == DW_PSEQ_ST_GOOD,
> +				10000, 1000000, false,
> +				xpcs, DW_VR_XS_PCS_DIG_STS);
> +	if (ret < 0)
> +		pr_err("%s: xpcs power-up timeout\n", __func__);

dev_err(). xpcs->mdiodev->dev.

You want to know which pcs returned an error. Always use dev_err() in
preference to pr_err()

	Andrew