netdev - RE: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functions

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Message-ID:
 <AM0PR04MB6289323F6F93E197103A225D8F05A@AM0PR04MB6289.eurprd04.prod.outlook.com>
Date: Mon, 31 Jul 2023 14:58:21 +0000
From: Leo Li <leoyang.li@....com>
To: Andrew Lunn <andrew@...n.ch>
CC: Heiner Kallweit <hkallweit1@...il.com>, Russell King
	<linux@...linux.org.uk>, "David S . Miller" <davem@...emloft.net>, Jakub
 Kicinski <kuba@...nel.org>, David Bauer <mail@...id-bauer.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Viorel Suman
	<viorel.suman@....com>, Wei Fang <wei.fang@....com>
Subject: RE: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functions



> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Saturday, July 29, 2023 3:14 AM
> To: Leo Li <leoyang.li@....com>
> Cc: Heiner Kallweit <hkallweit1@...il.com>; Russell King
> <linux@...linux.org.uk>; David S . Miller <davem@...emloft.net>; Jakub
> Kicinski <kuba@...nel.org>; David Bauer <mail@...id-bauer.net>;
> netdev@...r.kernel.org; linux-kernel@...r.kernel.org; Viorel Suman
> <viorel.suman@....com>; Wei Fang <wei.fang@....com>
> Subject: Re: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functions
> 
> On Fri, Jul 28, 2023 at 04:53:19PM -0500, Li Yang wrote:
> > In commit 7beecaf7d507 ("net: phy: at803x: improve the WOL feature"),
> > it seems not correct to use a wol_en bit in a 1588 Control Register
> > which is only available on AR8031/AR8033(share the same phy_id) to
> > determine if WoL is enabled.  Change it back to use
> > AT803X_INTR_ENABLE_WOL for determining the WoL status which is
> > applicable on all chips supporting wol. Also update the
> > at803x_set_wol() function to only update the 1588 register on chips having
> it.
> 
> Do chips which do not have the 1588 register not have WoL? Or WoL
> hardware is always enabled, but you still need to enable the interrupt.

Some of them do and some don't, which is removed in the other patch from the series.  Since I don't find the register to enable it, I guess it always enabled.

> 
> Have you tested on a range of PHY? It might be better to split this patch up a
> bit. If it causes regressions, having smaller patches can make it easier to find
> which change broken it.

No, I only have AR8035 to test with.  Changes for other chips are according to the datasheet.  It would be good if others having the hardware can test it too.

The problem right now on our board with AR8035 is that it gets the wrong WoL setting and fails to enter sleep:
[  354.196156] Qualcomm Atheros AR8035 0x0000000008b96000:02: PM: dpm_run_callback(): mdio_bus_phy_suspend+0x0/0x110 returns -16
[  354.196172] Qualcomm Atheros AR8035 0x0000000008b96000:02: PM: failed to suspend: error -16

Regards,
Leo