netdev - Re: [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks

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Message-ID: <dd34fa03-0b34-44a4-9e70-9d9a69f95403@lunn.ch>
Date: Tue, 1 Aug 2023 11:33:39 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Herve Codina <herve.codina@...tlin.com>
Cc: "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Qiang Zhao <qiang.zhao@....com>, Li Yang <leoyang.li@....com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>, Jaroslav Kysela <perex@...ex.cz>,
	Takashi Iwai <tiwai@...e.com>,
	Shengjiu Wang <shengjiu.wang@...il.com>,
	Xiubo Li <Xiubo.Lee@...il.com>, Fabio Estevam <festevam@...il.com>,
	Nicolin Chen <nicoleotsuka@...il.com>,
	Christophe Leroy <christophe.leroy@...roup.eu>,
	Randy Dunlap <rdunlap@...radead.org>, netdev@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, alsa-devel@...a-project.org,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available
 timeslots masks

On Wed, Jul 26, 2023 at 05:02:04PM +0200, Herve Codina wrote:
> Available timeslots masks define timeslots available for the related
> channel. These timeslots are defined by the QMC binding.
> 
> Timeslots used are initialized to available timeslots but can be a
> subset of available timeslots.
> This prepares the dynamic timeslots management (ie. changing timeslots
> at runtime).
> 
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> ---
>  drivers/soc/fsl/qe/qmc.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 2d2a9d88ba6c..21ad7e79e7bd 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -177,7 +177,9 @@ struct qmc_chan {
>  	struct qmc *qmc;
>  	void __iomem *s_param;
>  	enum qmc_mode mode;
> +	u64	tx_ts_mask_avail;
>  	u64	tx_ts_mask;
> +	u64	rx_ts_mask_avail;
>  	u64	rx_ts_mask;

Is this for E1? So there is a maximum of 32 slots? A u32 would be
sufficient i think?

	   Andrew