netdev - [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform

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Message-Id: <20230801010234.792557-1-niravkumar.l.rabara@intel.com>
Date: Tue,  1 Aug 2023 09:02:29 +0800
From: niravkumar.l.rabara@...el.com
To: niravkumar.l.rabara@...el.com
Cc: adrian.ho.yin.ng@...el.com,
	andrew@...n.ch,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	dinguyen@...nel.org,
	krzysztof.kozlowski+dt@...aro.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	mturquette@...libre.com,
	netdev@...r.kernel.org,
	p.zabel@...gutronix.de,
	richardcochran@...il.com,
	robh+dt@...nel.org,
	sboyd@...nel.org,
	wen.ping.teh@...el.com
Subject: [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform

From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>

patch [1/5] - Introduced compatible string for Agilex5 board.
patch [2/5] - Add Agilex5 reset ID definitions.
patch [3/5] - Add Agilex5 clock manager header and yaml file.
patch [4/5] - Reused and modified Agilex clock manager driver for
Agilex5 to avoid code duplication. This patch depends on patch 4.
patch [5/5] - Add device tree files for Agilex5 platform. This patch
depends on patch 1,2,3 & 4.

patch v2 changes:-
- Add separate discription and const for Agilex5 board in yaml file.
- Add reset ID definitions required for Agilex5 and reused
  altr,rst-mgr-s10 bindings similar to Agilex.
- Instead of creating separate clock manager driver, re-use agilex clock
  manager driver and modified it for agilex5 changes to avoid code
  duplicate.
- Fixed device tree alignment issues and other build warnings.
  Removed ethernet nodes as it will be included in a separate patch.

Niravkumar L Rabara (5):
  dt-bindings: intel: Add Intel Agilex5 compatible
  dt-bindings: reset: add reset IDs for Agilex5
  dt-bindings: clock: add Intel Agilex5 clock manager
  clk: socfpga: agilex: add clock driver for the Agilex5
  arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA

 .../bindings/arm/intel,socfpga.yaml           |   5 +
 .../bindings/clock/intel,agilex5-clkmgr.yaml  |  41 ++
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 ++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  39 ++
 drivers/clk/socfpga/clk-agilex.c              | 433 +++++++++++++++-
 .../dt-bindings/clock/intel,agilex5-clkmgr.h  | 100 ++++
 include/dt-bindings/reset/altr,rst-mgr-s10.h  |   5 +-
 8 files changed, 1089 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
 create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h

-- 
2.25.1