netdev - [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset

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Date: Thu,  3 Aug 2023 19:29:27 +0800
From: Feiyang Chen <chenfeiyang@...ngson.cn>
To: andrew@...n.ch,
	hkallweit1@...il.com,
	peppe.cavallaro@...com,
	alexandre.torgue@...s.st.com,
	joabreu@...opsys.com,
	chenhuacai@...ngson.cn
Cc: Feiyang Chen <chenfeiyang@...ngson.cn>,
	linux@...linux.org.uk,
	dongbiao@...ngson.cn,
	loongson-kernel@...ts.loongnix.cn,
	netdev@...r.kernel.org,
	loongarch@...ts.linux.dev,
	chris.chenfeiyang@...il.com
Subject: [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset

DMA reset on some platforms may fail, so add the dma_reset_times
variable to control the number of retries.

Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
---
 .../ethernet/stmicro/stmmac/dwmac1000_core.c    |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 17 +++++++++++------
 include/linux/stmmac.h                          |  1 +
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index abcce58e9c29..ad712e337a50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -541,6 +541,9 @@ int dwmac1000_setup(struct stmmac_priv *priv)
 	else
 		priv->plat->dwmac_regs = &dwmac_default_dma_regs;
 
+	if (!priv->plat->dma_reset_times)
+		priv->plat->dma_reset_times = 1;
+
 	priv->dev->priv_flags |= IFF_UNICAST_FLT;
 	mac->pcsr = priv->ioaddr;
 	mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index fc0da4336e4e..de1b1844bb8a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -176,15 +176,20 @@ const struct dwmac_regs dwmac_loongson64_dma_regs = {
 
 int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
 {
+	int err;
+	int cnt = priv->plat->dma_reset_times;
 	u32 value = readl(ioaddr + DMA_BUS_MODE);
 
-	/* DMA SW reset */
-	value |= DMA_BUS_MODE_SFT_RESET;
-	writel(value, ioaddr + DMA_BUS_MODE);
+	do {
+		value |= DMA_BUS_MODE_SFT_RESET;
+		writel(value, ioaddr + DMA_BUS_MODE);
 
-	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
-				 !(value & DMA_BUS_MODE_SFT_RESET),
-				 10000, 200000);
+		err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
+					 !(value & DMA_BUS_MODE_SFT_RESET),
+					 10000, 200000);
+	} while (cnt-- && err);
+
+	return err;
 }
 
 /* CSR1 enables the transmit DMA to check for new descriptor */
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index e1b9ddf83fe5..ad2905cd226c 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -357,5 +357,6 @@ struct plat_stmmacenet_data {
 	bool has_integrated_pcs;
 	const struct dwmac_regs *dwmac_regs;
 	bool fix_channel_num;
+	bool dma_reset_times;
 };
 #endif
-- 
2.39.3