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Message-Id: <a40bf8242d1805c94a1ff1a8762b87c7622cc1af.1691047285.git.chenfeiyang@loongson.cn>
Date: Thu, 3 Aug 2023 19:28:05 +0800
From: Feiyang Chen <chenfeiyang@...ngson.cn>
To: andrew@...n.ch,
hkallweit1@...il.com,
peppe.cavallaro@...com,
alexandre.torgue@...s.st.com,
joabreu@...opsys.com,
chenhuacai@...ngson.cn
Cc: Feiyang Chen <chenfeiyang@...ngson.cn>,
linux@...linux.org.uk,
dongbiao@...ngson.cn,
loongson-kernel@...ts.loongnix.cn,
netdev@...r.kernel.org,
loongarch@...ts.linux.dev,
chris.chenfeiyang@...il.com
Subject: [PATCH v3 03/16] net: stmmac: dwmac1000: Add multi-channel support
Some platforms have dwmac1000 implementations that support multi-
channel. Extend the functions to add multi-channel support.
Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
---
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 70 +++++++++++++++++--
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 37 ++++++----
2 files changed, 86 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 3996dea4b1e3..4cec78180556 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -114,15 +114,65 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
writel(mask, ioaddr + DMA_INTR_ENA);
}
+static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ u32 chan)
+{
+ u32 value;
+ int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
+ int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 mask = priv->plat->dwmac_regs->intr_ena->default_mask;
+
+ if (!priv->plat->multi_msi_en)
+ return;
+
+ /* common channel control register config */
+ value = readl(ioaddr + DMA_BUS_MODE + chan * offset);
+
+ /*
+ * Set the DMA PBL (Programmable Burst Length) mode.
+ *
+ * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
+ * post 3.5 mode bit acts as 8*PBL.
+ */
+ if (dma_cfg->pblx8)
+ value |= DMA_BUS_MODE_MAXPBL;
+ value |= DMA_BUS_MODE_USP;
+ value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
+ value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
+ value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
+
+ /* Set the Fixed burst mode */
+ if (dma_cfg->fixed_burst)
+ value |= DMA_BUS_MODE_FB;
+
+ /* Mixed Burst has no effect when fb is set */
+ if (dma_cfg->mixed_burst)
+ value |= DMA_BUS_MODE_MB;
+
+ value |= DMA_BUS_MODE_ATDS;
+
+ if (dma_cfg->aal)
+ value |= DMA_BUS_MODE_AAL;
+
+ writel(value, ioaddr + DMA_BUS_MODE + chan * offset);
+
+ /* Mask interrupts by writing to CSR7 */
+ writel(mask, ioaddr + DMA_INTR_ENA + chan * offset);
+}
+
static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
u32 addr = priv->plat->dwmac_regs->addrs->rcv_base_addr;
/* RX descriptor base address list must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + addr);
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addr + chan * offset);
}
static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
@@ -130,10 +180,11 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_tx_phy, u32 chan)
{
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
u32 addr = priv->plat->dwmac_regs->addrs->tx_base_addr;
/* TX descriptor base address list must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + addr);
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr + chan * offset);
}
static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
@@ -161,7 +212,8 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * offset);
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable RX store and forward mode\n");
@@ -183,14 +235,15 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
/* Configure flow control based on rx fifo size */
csr6 = dwmac1000_configure_fc(csr6, fifosz);
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CONTROL + channel * offset);
}
static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * offset);
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable TX store and forward mode\n");
@@ -217,7 +270,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
csr6 |= DMA_CONTROL_TTC_256;
}
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CONTROL + channel * offset);
}
static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
@@ -280,12 +333,15 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 riwt, u32 queue)
{
- writel(riwt, ioaddr + DMA_RX_WATCHDOG);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+
+ writel(riwt, ioaddr + DMA_RX_WATCHDOG + queue * offset);
}
const struct stmmac_dma_ops dwmac1000_dma_ops = {
.reset = dwmac_dma_reset,
.init = dwmac1000_dma_init,
+ .init_chan = dwmac1000_dma_init_channel,
.init_rx_chan = dwmac1000_dma_init_rx,
.init_tx_chan = dwmac1000_dma_init_tx,
.axi = dwmac1000_dma_axi,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 6411be0f3612..cf9e3e7b6b3f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -103,63 +103,71 @@ int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 chan)
{
- writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+
+ writel(1, ioaddr + DMA_XMT_POLL_DEMAND + chan * offset);
}
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_INTR_ENA + chan * offset);
if (rx)
value |= DMA_INTR_DEFAULT_RX;
if (tx)
value |= DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_INTR_ENA + chan * offset);
}
void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_INTR_ENA + chan * offset);
if (rx)
value &= ~DMA_INTR_DEFAULT_RX;
if (tx)
value &= ~DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_INTR_ENA + chan * offset);
}
void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value |= DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value &= ~DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value |= DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value &= ~DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
#ifdef DWMAC_DMA_DEBUG
@@ -238,9 +246,10 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir)
{
const struct dwmac_dma_status *status = priv->plat->dwmac_regs->status;
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
int ret = 0;
/* read the status register (CSR5) */
- u32 intr_status = readl(ioaddr + DMA_STATUS);
+ u32 intr_status = readl(ioaddr + DMA_STATUS + chan * offset);
#ifdef DWMAC_DMA_DEBUG
/* Enable it to monitor DMA rx/tx status in case of critical problems */
--
2.39.3
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