lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <wlx5q5v7isdnbbmf2xvhumj6ycakqufyzttqzlkfphfba4yw2u@n6krstdzb4d2> Date: Mon, 7 Aug 2023 16:13:55 -0500 From: Andrew Halaney <ahalaney@...hat.com> To: Bartosz Golaszewski <brgl@...ev.pl> Cc: Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Alex Elder <elder@...aro.org>, Srini Kandagatla <srinivas.kandagatla@...aro.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, netdev@...r.kernel.org, Bartosz Golaszewski <bartosz.golaszewski@...aro.org> Subject: Re: [PATCH 2/9] arm64: dts: qcom: sa8775p: add a node for EMAC1 On Mon, Aug 07, 2023 at 09:35:00PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org> > > Add a node for the second MAC on sa8775p platforms. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org> Reviewed-by: Andrew Halaney <ahalaney@...hat.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 38d10af37ab0..82af2e6cbda4 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -2325,6 +2325,40 @@ cpufreq_hw: cpufreq@...91000 { > #freq-domain-cells = <1>; > }; > > + ethernet1: ethernet@...00000 { > + compatible = "qcom,sa8775p-ethqos"; > + reg = <0x0 0x23000000 0x0 0x10000>, > + <0x0 0x23016000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + > + clocks = <&gcc GCC_EMAC1_AXI_CLK>, > + <&gcc GCC_EMAC1_SLV_AHB_CLK>, > + <&gcc GCC_EMAC1_PTP_CLK>, > + <&gcc GCC_EMAC1_PHY_AUX_CLK>; > + > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "phyaux"; > + > + power-domains = <&gcc EMAC1_GDSC>; > + > + phys = <&serdes1>; > + phy-names = "serdes"; > + > + iommus = <&apps_smmu 0x140 0xf>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <16384>; > + tx-fifo-depth = <16384>; > + > + status = "disabled"; > + }; > + > ethernet0: ethernet@...40000 { > compatible = "qcom,sa8775p-ethqos"; > reg = <0x0 0x23040000 0x0 0x10000>, > -- > 2.39.2 >
Powered by blists - more mailing lists